Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

www.quicklogic.com 78

For Clock domains 01, 09 and 10, the clock phase is locked, but the frequency may be different, such as Clock domain C30

and C31. For Clock C08X4 and C08X1, the clock phase is locked and the frequency of C08X1 is always one-fourth of C08X4

clock frequency.

Most Clock paths can be gated by software independently, the exceptions are Clock C00_P0, C01_P0, C10_HCLK_P0,

C10_FCLK_P0, C20_P0 and C23_P0. Software can also gate off the clock domains individually. For Clock domains C40 and

C41, the clock gating scheme depends on the design inside the on-chip programmable logic.

7.8.2. Resets

Each Clock path has its corresponding Reset Path. Most of them are asynchronous asserted and synchronous released

except for the Reset path for non-free running clock domains (e.g., clock paths from IOs, such as C00, C40, C41, CS and

C32). The reset for the M4-F core will is not de-asserted until the clock is toggled for a minimum of four cycles.

There are two possible global reset sources:

• Power-ON-Reset

• SYS_RSTn (System Reset)

After booting up, software can program a PMU register to block the SYS_RSTn (System Reset) and treat it as one of the

interrupt sources. The software can also reset some of the modules such as Voice Support by programming register bits.

For details about the PMU register, see the

QuickLogic E0S S3 Registers