Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 76
PKT FIFO (FFE clk)
10 MHz C08 X1_P3_PF
M4-F Subsystem Domain
M4-Complex: M4-F
subsystem, M4-AHB switch
(AHB clock)
80 MHz C10 HCLK_P0_M4
FCLK_P0_M4
M4-Complex: UART, WDT1,
Timer1 (APB clock 0)
10 MHz C11 P0_M4
M4-Complex: to Voice SS
and CFG_CTL (APB clock 1)
80 MHz C10 FCLK_PS_AD0
M4 CFG_CTL to FPGA (APB
clock)
10 MHz C09 P2_FB
A0 (AHB clock M4)
80 MHz C10 FCLK_P6_A0
M4 SWD (DA pin)
20 MHz CS P0_M4
SRAM Domain
SRAM 128 Kbyte instance 0
(AHB clock)
80 MHz C10 FCLK_P1_MS0
SRAM 128 Kbyte instance 1
(AHB clock)
80 MHz C10 FCLK_P2_MS1
SRAM 128 Kbyte instance 2
(AHB clock)
80 MHz C10 FCLK_P3_MS2
SRAM 128 Kbyte instance 3
(AHB clock)
80 MHz C10 FCLK_P4_MS3
Voice Subsystem Domain
Voice SS (AHB clock)
80 MHz C10 FCLK_P5_AD0
The ratio between the Voice SS AHB
and APB clock must be an integer
ratio, such as 1-1, 1-2, 1-4.
Voice SS (APB clock)
10 MHz C09 P0_AD5
PDM left clock
5 MHz C30 P0_AD1
PDM right clock
5 MHz C30 P1_AD2
I
2
S clock
5 MHz C30 P2_AD4
LPSD clock
1 MHz C31 P3_AD3
FPGA Domain
FPGA
72 MHz C16 P0_FB
Using on board HOSC output
FPGA
72 MHz C21 P0_FB
Using on board HOSC output
AHB2WB for FPGA clock
10 MHz C40 P0_FB
FPGA to Packet FIFO clock
20 MHz C41 P0_FB
a. Maximum frequency is with VDD = 1.1V ±10%.
Clock domains are numbered in sequence (e.g., C00, C01, C02, and so on). Individual clock paths in a single clock domain
are numbered (e.g., P0_A0, P1_A0, and so on). There can be similar clock path names, but they must be in different clock
domains (e.g., C00 P0_A0, C01 P0_A0).
For most of the clock domains, there are three possible sources:
• Fast Clock Driving from IO_6 - FCLK
• Real-Time Clock (RTC - 32 kHz)
• Oscillator Clock (OSC - Max. is 80 MHz). See the following figure for details.