Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 75
Clocks and Resets
7.8.1. Clocks
The EOS S3 platform contains 19 clock domains, and most clock domains have their own register-controlled divider. Each
clock domain has one or more clock paths that it supports. Clock paths can be individually gated. See the following table
for a full listing of clock domains.
Table 22: Clocks Listing
Block Name(s) Maximum
Frequency
a
Clock
Name
Clock Path Notes
Always-On Domain
AP to SPI_Slave, SPI_Slave
to TLC, TLC to PKT_FIFO
clock
20 MHz C00 P0_A0
TLC clock to AHB Switch
(AHB clock)
10 MHz C01 P0_A0 The AHB clock must be greater than or
equal to one half of the SPI Slave clock
(in line above).
AHB Switch, Reg Bank,
other blocks connected to
the switch on the Always-on
power domain
10 MHz C01 P0_A0
A1 Domain
CfgSM, CfgDMA, SPI_Master
(APB clock)
40 MHz C02 P0_A1
CfgDMA (AHB clock)
10 MHz C01 P4_A1
SPI_Master serial data clock
20 MHz C02 n/a
The SPI_Master serial clock frequency
is one half of the C02 clock frequency.
I
2
S Domain
I
2
S Slave (DA pin)
10 MHz C32 P0_I2S
I
2
S Slave APB interface
10 MHz C01 P5_I2S
SDMA Domain
AHB2APB, SDMA (AHB
clock)
10 MHz C01 P6_SDMA
SDMA SRAM Domain
SDMA SRAM
10 MHz C01 P1_A0
FFE Domain
AHB switch
10 MHz C01 P3_FFE
X1 clk
10 MHz C08 X1_P0_FFE
X4 clk
40 MHz C08 X4_P0_FFE
For A0
10 MHz C08 X1_P2_A0
For PKT FIFO
10 MHz C08 X1_P3_PF
Packet FIFO Domain
PKT FIFO (AHB clock)
10 MHz C01 P2_PF
PKT FIFO (TLC clock)
20 MHz C00 P0_A0
PKT FIFO (FPGA clock)
20 MHz C41 n/a
Generate inside FPGA using C16