Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 74
Power-Down Sequence of Crystal Clock
The recommended power-down sequence of the EOS S3 when crystal clock is used as input to XTAL_IN is shown in the
following figure.
Figure 47: Power-Down Sequence of Crystal Clock
Crystal Clock (32 kHz)
AVDD
LDO_VIN/VDD1/
VDD2
VCCIO
A
NOTE: Recommended power down sequence: VCCIO > VDD/AVDD. Power down VCCIO before VDD. Powering down all
power supplies at same time is allowed. Powering down AVDD/VCCIO together then VDD is allowed.
When the system requires intermittent power up/down, the power down duration for AVDD, ramp time, and
temperature of the input crystal clock are shown in the following table.
Table 21: Power-Down Duration Time for AVDD
AVDD Ramp Up Time Temperature AVDD Power-Down Time AVDD @ 90% to HOSC Lock
a
3.3 V Any
–20
℃
or higher
Not required Not more than 1.5 seconds
1.8 V Any
–20
℃
to less than 0
℃
More than 40 seconds Not more than 1.5 seconds
1.8 V Any
0
℃
to less than 25
℃
More than 5 seconds Not more than 1.5 seconds
1.8 V Any
25
℃
to 85
℃
More than 1 second Not more than 1.5 seconds
1.8 V Less than 100 µs –20
℃
to 85
℃
Power down must be less
than 100 milliseconds or
more than 1 second
Not more than 1.5 seconds
a. For more information, see row J in Table 20 .