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QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

www.quicklogic.com 73

Table 20: Power-On Sequence Timing Parameters

Letter Parameter Condition Min. Typ. Max. Unit

A AVDD Voltage Rising Time From 0 V to Target operating voltage See

Note

See

Note

See

Note

B LDO_VIN/VDD1/VDD2 Rising

Time

From 0 V to Target operating voltage See

Note

See

Note

See

Note

C VCCIOA/VCCIOB Rising Time From 0 V to Target operating voltage See

Note

See

Note

See

Note

µs

D Voltage Ready to SYS_RSTn

Release

All voltage rails at 90% voltage to

SYS_RSTn is released

300 – – µs

E SYS_RSTn Middle of the

Operation

SYS_RST_n assertion time 300 – – µs

F Voltage Ready to

HOST_SPI_Access Start

G System Reset Release to Chip

Exits Reset State

Chip ready 2 ms after SYS_RSTn

release

– – 2 ms

H Bootstrap pins setup time Setup time with respect to SYS_RSTn 1 – – µs

I Bootstrap pins hold time Hold time with respect to SYS_RSTn 1 – – µs

J HSOSC Lock High-speed oscillator lock – 500 1500

SPI Burst SPI burst access 500 – 1500

a. This is only required for a system that has intermittent power-down interruption. It is not required for AVDD always-on or

CMOS CLOCK always-on.

NOTE: For a system that has intermittent power up/down sequence, the AVDD rise time is recommended to be less than

100 µs. For more information, see Table 21.

NOTE: When using internal LDO for VDD, bring up AVDD, wait for LDO to ramp up to 90%, then bring up VCCIO. The

internal LDO starts to ramp up when the AVDD input reaches 1.5 V. The LDO takes up to 500 µS (max) to ramp up to 90%

of the target output level setting.

NOTE: Device initiation can begin after SYS_RSTn timing is met. SYS_RSTn signal is held low before power rails reach

90%. Initialization before SYS_RSTn timing is met can result in bootup failure. There is a weak pull-up inside SYS_RSTn,

see Table 35 for the resistance value.