Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 72
Power-On Sequence of Crystal Clock
The recommended power-on sequence of the EOS S3 when crystal clock is used as input to XTAL_IN is shown in the
following figure.
Figure 46: Power-On Sequence of Crystal Clock
XTAL_IN
XTAL_OUT
PAD(8) [Pull Down]
PAD(9) [Pull Down]
32.768 kHz
Clock
Host_SPI_Access Start
Host SPI (AP) Access
SYS_RSTn
CRYSTAL IN
VCCIO
LDO_VIN/VDD1/VDD2
AVDD
500 ms (Min.)
Reset during middle of operation
300 µs (Min.)
300 µs
(Min.)
2 ms
(Max.)
Boot Strap Pins
Boot Value
1 µs
(Min)
1 µs
(Min)
Do Not Care
Do Not Care
XTAL_IN
Chip ready 2 ms after
SYS_RSTn release
2 ms
G
The following figure shows the power-on sequence timing parameters.