Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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Power-Down Sequence of CMOS Clock

The recommended power-down sequence of the EOS S3 when CMOS clock is used as input to XTAL_IN is shown in the

following figure.

Figure 45: Power-Down Sequence of CMOS Clock

CMOS Clock (32 kHz)

AVDD

LDO_VIN/VDD1/

VDD2

VCCIO

3 ms

(Min)

2 ms

(Min)

NOTE: Recommended power down sequence: VCCIO > VDD/AVDD. Power down VCCIO before VDD. Powering down all

power supplies at same time is allowed. Powering down AVDD/VCCIO together then VDD is allowed.

NOTE: For AVDD, ensure that the CMOS clock is active during AVDD ramp down and after 2 ms AVDD is powered down.

Refer to Table 12 for AVDD. This is only required for a system that has intermittent power-down interruption for battery

savings. It is not required for AVDD always-on or CMOS CLOCK always-on or when using XTAL. For power-on sequence

refer to Table 9.

The following table lists the power-down sequence timing parameters.

Table 15: Power-Down Sequencing Timing Parameters

Letter Parameter Condition Min. Typ. Max. Unit

A AVDD Voltage Power-Down

Duration Time

AVDD Voltage Power-Down Duration

Time

3.0 - - ms

B CMOS CLOCK is active after

AVDD is powered down

CMOS CLOCK is required to be active

for a minimum time if AVDD is powered

down

2.0 - - ms

This is only required for a system that has intermittent power-down interruption. It is not required for AVDD always-on or CMOS

CLOCK always-on.

The following table lists the current measurement on voltage rail after power down with active CMOS clock.

Table 16: Current Measurements for Power-Down

Power Sequence AVDD 1.8V VDD 1.1V VCCIOB 1.1V VCCIOA 1.1V

IDD with CMOS clock active –2.8 mA 0 0 0

Typical values are based on 25°C and nominal voltage (VDD1=VDD2=1.1V, VCCIO=1.8V).

The following two tables list the typical inrush current for each mode with one voltage rail power up.