Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 66
Figure 41: Use Case 2: Single Voltage Rail
1.057 V – 1.132 V
1.057 V – 1.132 V
1.62 V – 3.6 V
1.62 V – 3.6 V
7.3.3. Use Case 3: External Voltage Supplied
In this example, the EOS S3 platform LDOs are bypassed and the SRAMs and logic gates are externally supplied through
VDD1 and VDD2 pads. The LDO_VIN, VDD2, and VDD1 pads are tied together on the board and connected to the supply
voltage.
NOTE: In this configuration, an external voltage of 1.1V ±50 mV is required to be applied to LDO_VIN, VDD1 and VDD2.
The device requires 1.05 V minimum to come out of Power-On reset. See Table 33 for DC specifications.
For bypass configuration, external power supplies are used. Therefore, turn off the internal LDOs using the firmware to
reduce the device core power consumption.
Figure 42: Use Case 3: External Voltage Supplied
1.62 V – 3.6 V
1.1 V
1.1 V
1.1 V