Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

www.quicklogic.com 62

6.3.3. SDMA Interface

The EOS S3 platform provides a System DMA (SDMA) module for use by various components. The purpose for the SDMA

function is to avoid loading the Host processor with simple data movement operations, and to conduct data movement

during periods when the Host Processor is in a low-power state.

For the IP in the on-chip programmable logic, the SDMA interface provides the means to process a block of data and

transfer the results to M4-F memory. Examples of this include:

• IP using SDMA to move data from M4-F memory, processing the data, and initiating SDMA to move this finished

result back to M4-F memory.

• IP reading data from an external sensor (e.g., through the SPI Master for System Support), processing the data,

and using an SDMA operation to save the results to M4-F memory.

After the SDMA operation is completed, an interrupt from the SDMA can signal the Host that the operation is completed.

Alternately, the IP in the on-chip programmable logic can also issue its own interrupt to the EOS S3 platform to signal the

completion of its processing operation.

It is important to note that the SDMA module resides at the EOS S3 platform level. Therefore, it can access the M4-F

Memory modules and the on-chip programmable logic IP. However, the IP cannot directly access the M4-F Memory

modules.

6.3.4. Interrupt Interface

The EOS S3 platform provides a set of interrupt signals to the on-chip programmable logic IP. These interrupt signals

enable the IP to signal to the EOS S3 platform that it needs attention. The nature of this attention depends upon the IP

and the nature of the required processing.

6.3.5. Sensor Processing Subsystem Interface

The Sensor Processing Subsystem can drive IP residing in the on-chip programmable logic with a Start signal and sample a

Busy status signal. These signals enable the IP to coordinate its processing with that of the Sensor Processing Subsystem.

This allows both modules to provide processed data to the EOS S3 platform for further evaluation or Sensor Fusion

processing.

It is important to note that there is no direct connection between the Sensor Processing Subsystem and the on-chip

programmable logic for the passing either processed or raw data. Instead, the data must first be passed to the EOS S3

platform (e.g., the M4-F Memory) before it can be passed to either the Sensor Processing Subsystem (e.g., from the on-

chip programmable logic IP) or to the on-chip programmable logic IP (e.g., from the Sensor Processing Subsystem).

6.3.6. Packet FIFO Interface

IP within the on-chip programmable logic can pass data to the EOS S3 platform via the Packet FIFO interface. Like the

Sensor Processing Subsystem, the IP logic can write raw or processed data into the Packet FIFO in a software-defined

packet format.

It is important to note that the Sensor Processing Subsystem and on-chip programmable logic-based IP do not share the

same connection to the Packet FIFO. Rather, each module uses a separate port to connect to the Packet FIFO. However,

within the Packet FIFO, each port must be assigned by software to a separate internal FIFO (e.g., the Packet FIFO is

composed of sub-FIFO 8K, 0, 1, and 2).