Datasheet
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation
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Interface to the On-Chip Programmable Logic
IP within the on-chip programmable logic can use the following interfaces to communicate with resources outside of the
chip. These include:
• EOS S3 Platform
• SPI Master Interface for System Support
• Sensor Processing Subsystem
• Packet FIFO
These resources help the IP to coordinate its activities with other modules in the EOS S3 platform. Additionally, the IP
can call upon external resources to support its processing activities. The following sections describe the resources
available to the IP within the on-chip programmable logic. It is not essential that the IP within the on-chip programmable
logic use these interfaces.
6.3.1. EOS S3 Platform Interface
The interface between IP in the on-chip programmable logic and the EOS S3 platform consists of the following:
• Data transfer interface via an AHB-to-Wishbone bridge
• SDMA interface
• Interrupt interface
6.3.2. AHB-To-Wishbone Bridge
The AHB-To-Wishbone Bridge provides the means for the EOS S3 platform (M4-F or AP) to access IP within the on-chip
programmable logic. Specifically, this interface takes a 32-bit address and data on its AHB port and passes these values
to the Wishbone bus. The following figure illustrates the AHB-to-Wishbone bridge.
Figure 39: AHB-to-Wishbone Bridge
Wishbone Bus
AHB Slave
AHB-to-Wishbone Bridge
EOS System
FPGA Fabric
The connection between the AHB Slave and Wishbone Bus supports asynchronous transfers. This allows the on-chip
programmable logic-based IP to use a clock frequency appropriate to its operation without the EOS S3 platform losing
its ability to communicate with the resources of the IP. For example, most IPs require the use of some type of Start or
Stop register bit to control their operations. The asynchronous interface ensures that the EOS S3 platform can still access
these registers.
It is important to note that the on-chip programmable logic-based IP does not have the ability to initiate direct transfers
to the EOS S3 platform. This is done for two reasons: first, the Wishbone bus cannot support multiple masters (the
Wishbone interface only supports Wishbone clients) and second, the AHB Slave interface cannot master the AHB bus.