Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 6
6.2.1. FIFO Controller .................................................................................................................................... 58
6.2.2. Configurable Input/Output Signals ...................................................................................................... 58
6.2.3. Multipliers ............................................................................................................................................ 59
Interface to the On-Chip Programmable Logic ....................................................................... 61
6.3.1. EOS S3 Platform Interface .................................................................................................................. 61
6.3.2. AHB-To-Wishbone Bridge ................................................................................................................... 61
6.3.3. SDMA Interface ................................................................................................................................... 62
6.3.4. Interrupt Interface ................................................................................................................................ 62
6.3.5. Sensor Processing Subsystem Interface ............................................................................................ 62
6.3.6. Packet FIFO Interface ......................................................................................................................... 62
7. Power Management ....................................................................................................... 63
Power Supply Modes and Schemes ...................................................................................... 63
SRAM Power Domains .......................................................................................................... 64
Low Dropout Regulators ........................................................................................................ 65
7.3.1. Use Case 1: Dual Voltage Rail Supplied by On-Chip LDOs ............................................................... 65
7.3.2. Use Case 2: Single Voltage Rail Supplied by Single On-Chip LDOs ................................................. 65
7.3.3. Use Case 3: External Voltage Supplied .............................................................................................. 66
Power-On Sequence of CMOS Clock .................................................................................... 67
Power-Down Sequence of CMOS Clock ................................................................................ 70
Power-On Sequence of Crystal Clock .................................................................................... 72
Power-Down Sequence of Crystal Clock ............................................................................... 74
Clocks and Resets ................................................................................................................. 75
7.8.1. Clocks .................................................................................................................................................. 75
7.8.2. Resets ................................................................................................................................................. 78
8. Other EOS S3 Platform Features .................................................................................. 79
Multi-Function Inputs/Outputs (IOs) ....................................................................................... 79
General Purpose Inputs/Outputs (GPIOs) .............................................................................. 79
Fabric Inputs/Outputs (FBIOs) ............................................................................................... 79
Interrupts ............................................................................................................................... 79
8.4.1. Interrupt Structure ............................................................................................................................... 79
8.4.2. Interrupt Sources ................................................................................................................................. 80
8.4.3. M4-F Wake-Up Events ........................................................................................................................ 81
Bootstrap Modes ................................................................................................................... 82
M4-F Serial Wire Debug Port Configuration ........................................................................... 82
8.6.1. Internal/External HSO Configuration ................................................................................................... 83
8.6.2. SWD Debugger Present Configuration ............................................................................................... 83
8.6.3. AP/Wearable Mode Configuration ....................................................................................................... 83
9. Other Peripherals ........................................................................................................... 84
Packet FIFO .......................................................................................................................... 84
9.1.1. FIFO_8K .............................................................................................................................................. 85
9.1.2. FIFO_0, FIFO_1, FIFO_2 .................................................................................................................... 85