Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 58
RAM/FIFO
The on-chip programmable logic also includes up to eight instances of 8K (9,216 bits) dual-port RAM modules for
implementing RAM and FIFO functions.
RAM features include:
• Independently configurable read and write data bus widths
• Independent read and write clocks
• Inverted or non-inverted clock signals to read and write clock inputs
• Horizontal and vertical concatenation
• Write byte enables
• Selectable pipelined or non-pipelined read data
6.2.1. FIFO Controller
Every 8K RAM block can also be implemented as a synchronous or asynchronous FIFO. There are built-in FIFO controllers
that allow for varying depths and widths without requiring on-chip programmable logic resources. During asynchronous
operation, the FIFO works in a half-duplex fashion such that PUSH is on one clock domain and POP is on another clock
domain. The DIR signal allows the FIFO PUSH and POP signal directions to reverse.
FIFO controller features include:
• x9, x18 and x36 data bus widths
• Independent PUSH and POP clocks
• Independent programmable data width on PUSH and POP sides
• Configurable synchronous or asynchronous FIFO operation
• 4-bit PUSH and POP level indicators to provide FIFO status outputs for each port
• Pipelined read data to improve timing
• Option for inverted or non-inverted asynchronous flush input
6.2.2. Configurable Input/Output Signals
Configurable IO interface provides additional functionality prior to driving the actual IO. This additional functionality is
comprised of the following:
• Register path versus nonregister path for IN, OUT, and EN
• FIX_HOLD feature to improve hold time
See the following figure for on-chip programmable logic configurable I/Os.