Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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• Direct input selection to the register, which allows combinatorial and register logic to be used separately

• Combinatorial logic can also be configured as an edge-triggered master-slave D flip-flop

Figure 36: Logic Cell Block Diagram

From Routing

QST

QDS

TBS

TAB

TSL

TA1

TA2

TB1

TB2

BAB

BSL

BA1

BA2

BB1

BB2

QDI

QEN

QCK

TAS1

TAS2

TBS1

TBS2

BAS1

BAS2

BBS1

BBS2

QCSK

QRT