Datasheet

www.quicklogic.com 56

6. On-Chip Programmable Logic

The on-chip programmable logic provides flexibility to the EOS S3 platform for implementing additional functions. The

on-chip programmable logic consists of multiplexor-based logic cells, built-in RAM modules and FIFO controllers, built-

in multipliers, as well as interfaces with I/O drivers of the EOS S3 device. The major features of the embedded on-chip

programmable logic are listed in the following figure.

Table 7: On-Chip Programmable Logic Major Features

Feature EOS S3

Logic Cells 891

8K RAM Modules (512x18 – 9,216 bits) 8

FIFO Controllers 8

RAM Bits 73,728

Configurable Interface 32

Multiplier 2x 32 x 32

4x 16 x 16

Highlight of FPGA performance:

Table 8: FPGA performance

Feature Data Note

16-bit synchronous counter 100 MHz Using external CLOCK input

Adjacent Flop to Flop delay 4.5ns

Functional Description

6.1.1. Logic Cell

Each logic cell is a multiplexer-based single register. The cell has a high fan-in and fits a wide range of functions with up

to 22 simultaneous inputs (including register control lines), and four outputs (three combinatorial and one registered).

The following figure illustrates the logic block structure. The high logic capacity and fan-in of the logic cell accommodates

many user functions with a single level of logic delay. The logic cell is capable of implementing the following functions:

• Two independent 3-input functions

• Any 4-input function

• 8 to 1 mux function

• Independent 2 to 1 mux function

• Inverted or non-inverted clock signal to flip-flop

• Single dedicated register with active high clock enable, set and reset signals