Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 55
5.4.2. SPI Slave
The following figure illustrates the SPI Slave timing.
Figure 35: SPI Slave Timing
SCL
CSn
MOSI
MISO
f
CLK
t
LOW
t
HIGH
t
DI:HOLD
t
DI:SETUP
t
DO:HOLD
t
DO:DELAY
t
CS:SETUP
t
CS:HOLD
t
CS:BUF
The following table lists the SPI Slave timing.
Table 6: SPI Slave Timing
Symbol Parameter Min. Max. Units
f
CLK
SPI Clock - 20 MHz
t
LOW
SPI Clock Low Time 22.5 - ns
t
HIGH
SPI Clock High Time 22.5 - ns
t
DO:SETUP
MISO Output Delay from SPI Clock Driving
Edge
- 16 ns
t
DO;HOLD
MISO Output Delay Hold Time 2 - ns
t
DI:SETUP
MOSI Input Setup Time 4 - ns
t
DI;HOLD
MOSI Input Hold Time 4 - ns
t
CS:SETUP
CS Input Setup Time 4 - ns
t
CS;HOLD
CS Input Hold Time 4 - ns
t
CS;BUFF
CS High Time 50 - ns