Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 54
Table 4: PDM Microphone Timing
Symbol Parameter Min. Typ. Max. Units
f
CLK
PDM Frequency - - 10 MHz
t
SU
Data Input Set Up Time 10 - - ns
t
H
Data Input Hold Time 1 - - ns
f
CLK
Duty Cycle 48 50 52 %
SPI Timing
5.4.1. SPI Master
The following figure illustrates the SPI Master timing.
Figure 34: SPI Master AC Timing
SCL
CSn
MOSI
MISO
f
CLK
t
LOW
t
HIGH
t
DO:HOLD
t
DO:SETUP
t
DI:SETUP
t
DI:HOLD
t
CS:SETUP
t
CS:HOLD
The following table lists the SPI Master timing.
Table 5: SPI Master Timing
Symbol Parameter Min. Max. Units
f
CLK
SPI Clock Frequency - 20 MHz
t
LOW
SPI CLK Low Time 24 - ns
t
HIGH
SPI CLK High Time 24 - ns
t
DO:SETUP
Data Output Setup Time to slave device
(2/ f
CLK
)-5
- ns
t
DO;HOLD
Data Output Hold Time 1.1 4.8 ns
t
DI:SETUP
Data Input Setup Time 8 - ns
t
DI;HOLD
Data Input Hold Time 1 - ns
t
CS:SETUP
CS Input Setup Time 50 - ns
t
CS;HOLD
CS Input Hold Time 50 - ns