Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 53
Figure 32: I
2
S Timing Waveform
Serial
Clock
(SCK)
Word
Select
(WS)
f
CLK
t
LOW
Data
In
Data
Out
t
LOW
t
D:DELAY
t
OH:OUTHOLD
LSB MSB
LSB
MSB
t
SU:SETUP
t
H:HOLD
Table 3: I
2
S Timing
Symbol Parameter Min. Typ. Max. Units
f
CLK
I
2
S Clock Frequency
- - 10 MHz
t
LOW
Clock High Period 45 - - ns
t
HIGH
Clock Low Period 45 - - ns
t
SU
Data Input Set Up Time 10 - - ns
t
H
Data Input Hold Time 1 - - ns
t
D
Clock to Data Out Delay 3 - 35 ns
t
OH
Clock to Out Hold 2 - - ns
PDM Microphone Timing
The following figure and table describe the PDM microphone timing.
Figure 33: PDM Microphone Timing
PDM_CKO
PDM_DIN (L/R = 0)
DATA
VALID
t
SU
t
H
PDM_DIN (L/R = 1)
DATA
VALID
DATA
VALID
t
SU
t
H
f
CLK