Datasheet

© 2020 QuickLogic Corporation www.quicklogic.com 52
5. Timing
I
2
C Master AC Timing
The following figure shows the I
2
C Master AC timing.
Figure 31: I
2
C Master AC Timing
SCL
SDA
SCL
SDA
t
HD:STA
t
HD:DAT
t
SU:DAT
t
LOW
t
HIGH
t
SU:STO
t
BUF
The following figure describes the I
2
C Master AC timing parameters.
Table 2: I
2
C Master AC Timing
Symbol Description Standard Mode Fast Mode Units
Min. Max. Min. Max.
f
SCL
Operating frequency. - 100 - 400 kHz
t
LOW
Clock low period. 4.7 - 1.30 - µs
t
HIGH
Clock high period. 4.0 - 0.60 - µs
t
HD;STA
Hold time for repeated START condition. 3.10 - 0.60 - µs
t
SU;STA
Setup time for repeated START condition. 4.19 - 0.60 - µs
t
BUF
Bus free time between STOP and START
condition.
4.7 - 1.3 - µs
a
t
HD;DAT
Data hold time. 0 - 0 - µs
t
SU;DAT
Data setup time. 0.25 - 0.10 - µs
t
SU;STO
Setup time for STOP. 4.0 - 0.6 - µs
a. The receiving device must provide an internal delay of 300 ns for the SDA signal with respect to the SCL signal to
bridge the undefined region of the falling edge of SCL.
I
2
S Timing
The following figure and table describe the I
2
S timing.