Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 5
3.5.5. SPI Slave ............................................................................................................................................. 36
3.5.6. SPI Interface Protocol ......................................................................................................................... 38
3.5.7. Basic Read/Write Transfers ................................................................................................................ 38
3.5.8. Device ID Read ................................................................................................................................... 39
3.5.9. Transfer Types .................................................................................................................................... 39
3.5.10. Transfers to TLC Local Registers ..................................................................................................... 40
3.5.11. Transfers from Packet FIFOs ............................................................................................................ 40
3.5.12. Transfers to M4-F Memory Address Space ...................................................................................... 40
3.5.13. Basic AHB Transfer Restrictions ....................................................................................................... 40
3.5.14. SPI Write Cycle ................................................................................................................................. 41
3.5.15. SPI Read Cycle ................................................................................................................................. 42
3.5.16. SPI Multiple Read Cycle .................................................................................................................... 42
3.5.17. SPI 3-Wire Configuration................................................................................................................... 43
3.5.18. SPI Corner Cases ............................................................................................................................. 43
3.5.19. Transmission Format ......................................................................................................................... 44
3.5.20. Clock Phase and Polarity Controls .................................................................................................... 45
AHB Master Bridge ................................................................................................................ 48
Control Registers ................................................................................................................... 48
Packet FIFO .......................................................................................................................... 48
On-Chip Programmable Logic ............................................................................................... 48
4. Voice Subsystem ........................................................................................................... 49
PDM Microphone ................................................................................................................... 49
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S Microphones .................................................................................................................... 49
Low Power Sound Detect Support ......................................................................................... 50
PDM Slave Port for External Codec ....................................................................................... 50
DMA and AHB Master Port .................................................................................................... 50
APB Slave Port ...................................................................................................................... 50
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S Slave Port ........................................................................................................................ 50
5. Timing ............................................................................................................................. 52
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C Master AC Timing ........................................................................................................... 52
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S Timing ............................................................................................................................. 52
PDM Microphone Timing ....................................................................................................... 53
SPI Timing ............................................................................................................................. 54
5.4.1. SPI Master ........................................................................................................................................... 54
5.4.2. SPI Slave ............................................................................................................................................. 55
6. On-Chip Programmable Logic ...................................................................................... 56
Functional Description ........................................................................................................... 56
6.1.1. Logic Cell ............................................................................................................................................. 56
RAM/FIFO ............................................................................................................................. 58