Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

www.quicklogic.com 47

This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and

shifting taking place on odd numbered edges. Data reception is double-buffered; data is serially shifted into the SPI shift

After the sixteenth SCK edge:

• Data that was previously in the SPI data register of the master is now in the data register of the slave, and

conversely, data that was in the data register of the slave is in the master.

• The SPIF flag bit in SPISR is set indicating that the transfer is complete.

The following figure shows two clocking variations for CPHA = 1. The diagram can be interpreted as a master or slave

timing diagram since the SCK, MISO, and MOSI pins are connected directly between the master and the slave.

The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave

select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output that

does not affect the SPI.

Figure 27: SPI Clock Format 1 (CPHA = 1)

Idle State Ends

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Transfer Begins

Transfer

Transfer Ends

Idle State Begins

Next Transfer Begins

SCK Edge Nr.

SCK (CPOL = 0)

SCK (CPOL = 1)

Sample 1

MOSI/MISO

Change O

MOSI Pin

Change O

MISO Pin

SEL SS (I)

SEL SS (O)

Master Only

In Figure 27, the following conditions apply:

MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB

LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB

— Minimum leading time before the first SCK edge, not required for back to back transfers

— Minimum trailing time after the last SCK edge

— Minimum idling time between transfers (minimum SS high time), not required for back to back transfers

and

must be at least ½ of SCK