Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

www.quicklogic.com 46

Figure 26: SPI Clock Format 0 (CPHA = 0)

Idle State Ends

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Transfer Begins

Transfer

Transfer Ends

Idle State Begins

Next Transfer Begins

SCK Edge Nr.

SCK (CPOL = 0)

SCK (CPOL = 1)

Sample 1

MOSI/MISO

Change O

MOSI Pin

Change O

MISO Pin

SEL SS (I)

SEL SS (O)

Master Only

In Figure 26, the following conditions apply:

MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB

LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB

— Minimum leading time before the first SCK edge

— Minimum trailing time after the last SCK edge

— Minimum idling time between transfers (minimum SS high time)

and

must be at least ½ of SCK. t

and

are guaranteed for the master mode and required for the slave mode.

3.5.20.2. CPHA = 1 Transfer Format

Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, and the second

edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of

the 8-cycle transfer operation.

The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the

slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears

on the SCK pin, which is the latching edge for both the master and slave.

When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of

the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial

data output pin of the master to the serial input pin on the slave.