Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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Figure 25: SPI Block Diagram

Shift Register

Master SPI Slave SPI

MISO

MOSI

SCK

Shift Register

Baud Rate Register

MISO

MOSI

SCK

3.5.20. Clock Phase and Polarity Controls

Using two bits in the SPI Control Register1, the software selects one of four combinations of serial clock phase and

polarity:

• The CPOL clock polarity control bit specifies an active high or low clock, neither of which significantly affects

the transmission format.

• The CPHA clock phase control bit selects one of two fundamentally different transmission formats.

Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases,

the phase and polarity may be changed between transmissions to allow a master device to communicate with peripheral

slaves that have different requirements.

3.5.20.1. CPHA = 0 Transfer Format

The first edge on the SCK line clocks the first data bit of the slave into the master, and the first data bit of the master into

the slave. In some peripherals, the first bit of the slave data is available at the slave data out pin as soon as the slave is

selected. In this format, the first SCK edge is issued a half cycle after SS has become low.

A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously

latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on Least Significant

Bit First Enable (LSBFE).

After this second edge, the next bit of the SPI Master data is transmitted out of the serial data output pin of the master

to the serial input pin on the slave. This process continues for 16 edges on the SCK line, with data being latched on odd

numbered edges, and shifted on even numbered edges.

Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer, and is transferred

to the parallel SPI data register after the last bit is shifted in. After the sixteenth (the last of the edges) on the SCK line:

• Data that was previously in the master SPI data register should now be in the slave data register, and conversely,

the data that was in the slave data register should be in the master SPI data register.

• The SPI Interrupt Flag (SPIF) in the SPI status register is set indicating that the transfer is complete.

The following figure shows a timing diagram of a SPI transfer where CPHA = 0, with SCK waveforms shown for CPOL = 0

and CPOL = 1. The diagram can be interpreted as a master or slave timing diagram since the SCK, MISO, and MOSI pins

are connected directly between the master and the slave.

The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master

must be set either high or reconfigured as a general-purpose output that does not affect the SPI.