Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

www.quicklogic.com 44

If the SPI interface is intended to support additional devices, such as SPI-based ACDs for measuring the output of

additional sensor types, then the number of potential non-byte aligned shift sequences increases significantly.

For example, the SPI transfer sequence corresponding to the AD7091 low power, 12-bit ADC is shown in the following

figure.

Figure 24: AD7091 SPI Transfer Sequence

NOTE: In Figure 24, EOC is the end of a conversation.

The preceding two figures show that the data portion of the transfer consists of values that are not a direct multiple of

8-bits. Therefore, the SPI transfer would need to first store the MSBs (e.g., DB[11:8] for the AD7091) using a shift

sequence of four SPI clock cycles prior to storing the LSB.

These are just a few of the potential corner cases that SPI-based devices may present. To support such cases, the

following capabilities have been added:

• Shift data based on 1 to 8 shift clock cycles

• Keep the Chip Select signal low between SPI transfer cycles

• Allow for running the SPI shift clock for a preset number of cycles after asserted

Some specific devices require additional shift clock cycles after Chip Select is removed (for example, to allow them to

achieve low power states or to complete a requested operation).

3.5.19. Transmission Format

During a SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The

serial clock (SCK) synchronizes both the shifting and the sampling of the information on the two serial data lines. A slave

select line allows for the selection of an individual slave SPI device (slave devices that are not selected do not interfere with

the ongoing SPI bus activities. The following figure shows the relationship between the SPI Master, SPI Slave, and the

related registers.