Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 43
Figure 21: SPI Multiple Read Operation (Mode 11)
SPI_CSn
SPI_CLK
MOSI
MOSI
Register Address (ADDR) Data 1 (from ADDR) Data 2 (from ADDR) Data 3 (from ADDR) Data 4 (from ADDR)
R/W AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI/07DI/06DI/05DI/04DI/03DI/02DI/01DI/O0 DI/07DI/06DI/05DI/04DI/03DI/02DI/01DI/O0 DI/07DI/06DI/05DI/04DI/03DI /02DI/01DI/O0 DI/07DI/06DI/05DI/04DI/03DI/02DI/01DI/O0
3.5.17. SPI 3-Wire Configuration
The following figure shows a basic SPI read/write operation under mode 11 (CPOL = 1, CPHA = 1) in a 3-wire configuration.
Figure 22: 3-Wire Basic SPI Read/Write Sequence (Mode 11)
SPI_CSn
SPI_CLK
MOSI
R/W AD6 AD5 AD4 AD3 AD2 AD1 AD0 DI/O7 DI/O6 DI/O5 DI/O4 DI/O3 DI/O2 DI/O1 DI/O0
3.5.18. SPI Corner Cases
There are cases where certain sensors do not support 8-bit data alignment. In the following example, this transfer
sequence comes from a muRata™ SCA100T-D07 2-Axis High Performance Analog Accelerometer, as shown in the following
figure.
Figure 23: muRata Command and 11-bit SPI Acceleration Data Read Sequence
SCB
SCK
MOSI
MISO
Command
High Impedance
0 1 2 3 4 5 6 7 8 9 10
10 9 8 7 6 5 4 3 2 1 0
11 12 13 14 15 16 17 18