Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 42
The following figure shows the basic SPI write operation under mode 11 (CPOL = 1, CPHA = 1).
Figure 19: Basic SPI Write Operation (Mode 11)
SPI_CSn
SPI_CLK
MOSI
MISO
R/W AD6 AD5 AD4 AD3 AD2 AD1 AD0
Z
Tri-state
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
3.5.15. SPI Read Cycle
The following figure shows the basic SPI read operation under mode 11 (CPOL = 1, CPHA = 1).
Figure 20: Basic SPI Read Operation (Mode 11)
SPI_CSn
SPI_CLK
MOSI
MISO
R/W AD6 AD5 AD4 AD3 AD2 AD1 AD0
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 TRI-STATE
3.5.16. SPI Multiple Read Cycle
The following figure shows SPI multiple read operations under mode 11 (CPOL = 1, CPHA = 1).
Multiple read operations are possible by keeping the SPI_CSn low and continuing the data transfer. Only the first register
address needs to be written. Addresses are automatically incremented after each read providing that the SPI_CSn line is
held low.