Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 41
register, the Memory Address Byte 0 – 1 registers are automatically incremented.
In addition, the TLC registers address loops back to point to the first data byte register, Memory Data Byte 0. By doing this,
a block of data may be written from a single SPI data stream (for example, one address phase followed by a series of data
phases representing the burst data).
See the following figure for an example of a burst write sequence.
Figure 17: SPI Master Burst Write Sequence
Address
Data Out
0
(Byte 0)
X X X X X
...
X X X
MOSI
MISO
Burst write data must always end on a 4 byte boundary
Burst Write Data Word 0
Data Out
1
(Byte 1)
Data Out
2
(Byte 2)
Data Out
3
(Byte 3)
Data Out
4
(Byte 0)
Data Out
n
(Byte 3)
AHB Memory write transfer block sizes are currently limited to 64K bytes (for example, 16K, 32-bit words). In addition,
access restrictions through the AHB Bridge require each transfer cannot consist of more than four bytes. Consequently,
writes to the TLC Memory Data Byte 3 register automatically trigger an increment by four in the TLC Memory Address Byte
0 – 1 registers, as well as triggering as data write through the AHB interface. The TLC Memory Address Bytes 2 – 3 registers
are not affected by writes to Memory Data Byte 3. Therefore, burst transfers that exceed the 64K byte boundary
automatically wrap back to the beginning.
3.5.13.2. AHB Memory Burst Read
To complement the Burst Write transfer in the previous section, the EOS S3 device also provides a Burst Read transfer
operation. Unlike the Burst Write, the EOS S3 device implements its Burst Read transfer as a DMA operation. Prior to
initiating Burst Read transfers, the software must first check the following conditions:
• If there is no Burst Read transfer underway: All of the data from the previous Burst Read transfer must first be
read out through the SPI Interface prior to initiating another Burst Read transfer.
• If there is data remaining in the Burst Read transfer FIFO: Check this by reading the Burst FIFO Status register.
Once both conditions are true, the Host can configure the Burst Read transfer by writing the target address into the TLC
Burst Read AHB Byte Address Byte 0 – 3 registers. This is followed by writing the data value into the TLC Burst Size Byte 0
register. The Burst Read begins with writing to the Burst Size Byte 1 register, and there needs to be two dummy byte
cycles following the write to the Burst Size Byte 1 register.
The simplest way to do this is by reading the Burst FIFO Status register, where this status is used to determine that there
is a minimum of one byte available to be read from the Burst Read Data register. If the minimum (one Burst Read data byte)
is available, the burst read operation begins by reading from the Burst Read Data register.
The TLC supports the burst transfer operation by not incrementing its register address pointer when it reads from the
Burst Read Data register. If a single word needs to be read, set both the Burst Size Byte 0 and 1 register to zero.
The following figure shows an example of the sequence.
Figure 18: Example Burst Read Sequence
X
Dummy
Address
(Reg. 0x40)
X X X X
...
X X X
MOSI
MISO
Burst write data must always end on a 4 byte boundary
Burst Read 32-Bit Word 0
Dummy
Data In
0
(Byte 0)
Data In
1
(Byte 1)
Data In
2
(Byte 2)
Data In
n
(Byte 3)
Data In
3
(Byte 3)
Data In
4
(Byte 0)
X X
3.5.14. SPI Write Cycle