Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 40
– Burst write transfers to the M4-F Memory space
– Burst read transfers from the M4-F Memory space
3.5.10. Transfers to TLC Local Registers
This transfer type depends upon the type of TLC register being accessed. The default TLC response is to increment
automatically the TLC register address (not the M4-F Memory space address) after each byte accessed (for example, as
in a read from the M4-F Memory Address registers). For details, see Figure 15, where the SPI protocol address phase
uses the address for the Memory Address Byte 0 register.
Once this transfer has completed, the TLC automatically increments its register address to Memory Address Byte 1.
Similarly, once this transfer has completed, the TLC automatically increments its register address to Memory Address Byte
2. This sequence repeats until all bytes are transferred or a TLC register address is reached that prevents this auto-
incrementing operation. For details about TLC register types that prevent auto-incrementing, see Transfers to M4-F
Memory Address Space.
NOTE: This auto-incrementing operation does not prevent any special features in these registers from being triggered. For
exceptions, see Basic AHB Transfer Restrictions.
3.5.11. Transfers from Packet FIFOs
Packet FIFOs accessible from within TLC can only be read from and cannot be written to. Therefore, any writes to the
Packet FIFOs are ignored. Conversely, since these are FIFOs, a burst read from these FIFOs requires that the same TLC
register address be accessed multiple times. As a result, the TLC does not increment its register address when accessing
any Packet FIFO address.
3.5.12. Transfers to M4-F Memory Address Space
The following sections outline the transfer types and restrictions when accessing the M4-F Memory Address space via
the AHB Bridge interface.
3.5.13. Basic AHB Transfer Restrictions
The TLC restricts AHB Memory transfers to 4 bytes per transfer cycle. No other transfer size is currently supported. The
following sections describe additional transfer specific restrictions.
• AHB Memory Burst Write
• AHB Memory Burst Read
3.5.13.1. AHB Memory Burst Write
All AHB write operations are done though programming TLC registers. A single write transfer is treated as a burst of one
32-bit word. To set up an AHB write operation, the Host needs to write the TLC AHB Access Control to 0x3.
Set up the target AHB address by writing to the TLC Memory Address Byte 3 – 0. Keep the TLC Memory Address Byte 0
as bits[1:0] to 0x3. For example, writing to address 0x20001040 means writing:
• TLC Memory Address Byte 0 to 0x43
• TLC Memory Address Byte 1 to 0x10
• TLC Memory Address Byte 2 to 0x00
• TLC Memory Address Byte 3 to 0x20
This is followed by writing the data value into the TLC Memory Data Byte 0 – 3. Upon writing to the Memory Data Byte 3