Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 4
Contents
QuickLogic EOS S3 Ultra Low Power multicore MCU Platform Highlights .................. 13
1. Functional Overview ...................................................................................................... 15
EOS S3 Ultra Low Power multicore MCU Platform Architecture ............................................ 15
2. M4-F Processor Subsystem .......................................................................................... 20
Subsystem Overview ............................................................................................................. 20
2.1.1. System-Level Interface ........................................................................................................................ 21
2.1.2. Integrated Configurable Debug ........................................................................................................... 21
2.1.3. M4-F and Core Peripherals ................................................................................................................. 21
2.1.4. Embedded SRAM ................................................................................................................................ 22
2.1.5. Development Support (Serial Wire Interface) ..................................................................................... 23
2.1.6. Debugger Bootstrap Configurations .................................................................................................... 24
3. Sensor Processing Subsystem .................................................................................... 25
Overview ............................................................................................................................... 25
Flexible Fusion Engine .......................................................................................................... 26
3.2.1. µDSP-Like Processor .......................................................................................................................... 26
3.2.2. Instruction Memory .............................................................................................................................. 27
3.2.3. Data Memory ....................................................................................................................................... 27
Sensor Manager .................................................................................................................... 27
3.3.1. Microcontroller Unit ............................................................................................................................. 28
3.3.2. Instruction and Data Memory .............................................................................................................. 28
I
2
C Master ............................................................................................................................. 29
3.4.1. System Configuration .......................................................................................................................... 30
3.4.2. I
2
C Protocol ......................................................................................................................................... 30
3.4.3. START Signal ...................................................................................................................................... 30
3.4.4. Slave Address Transfer ....................................................................................................................... 31
3.4.5. Data Transfer ...................................................................................................................................... 31
3.4.6. STOP Signal ........................................................................................................................................ 31
3.4.7. Arbitration ............................................................................................................................................ 31
3.4.8. I
2
C Core Architecture .......................................................................................................................... 31
3.4.9. Clock Generator .................................................................................................................................. 32
3.4.10. Byte Command Controller ................................................................................................................. 32
3.4.11. Bit Command Controller .................................................................................................................... 33
3.4.12. Data I/O Shift Register ...................................................................................................................... 33
Serial Peripheral Interface (SPI) ............................................................................................ 33
3.5.1. SPI Master for System Support ........................................................................................................... 34
3.5.2. SPI Master for System Support Features ........................................................................................... 34
3.5.3. Configuration Logic ............................................................................................................................. 35
3.5.4. SPI Master for Sensor Processing Subsystem Support ..................................................................... 36