Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 39
Figure 15: SPI Slave Protocol Diagram
7 6 5 4 3 2 1 0
Address Data In 1 Data In 1 ... Data In n
X X X X X
Address X X X X
X Dummy Dummy Data Out 0 ...
X
Data Out n
MOSI
MISO
MOSI
MISO
SPI Write
SPI Read
MSB LSB
Read/Write Bit
0 - Read
1 - Write
3.5.8. Device ID Read
The Device ID transfer cycle is a special protocol cycle for identifying the EOS S3 device to the Host SPI controller. Unlike the
write transfer cycle previously described, the address value of 0xFF indicates to the SPI Interface that an ID read cycle is
underway. In response, the SPI Interface returns an ID value 0x21 on the SPI_SLAVE_MISO pin one byte after the address
phase.
The following figure shows an example of the SPI Slave Device ID read protocol.
Figure 16: SPI Slave Device ID Read Protocol
0xFF X X
X Dummy 0x21
MOSI
MISO
3.5.9. Transfer Types
There are three basic transfer types supported:
• Transfers to TLC local registers — This transfer type accesses TLC local registers alone and does not produce
any activity on the AHB interface.
• Transfers from Packet FIFOs
 This transfer type accesses the TLC local registers. However, the goal is to read from the Packet FIFOs.
 The read transactions can be conducted as a single or as a burst transfer.
• Transfers to resources in the M4-F Memory address space.
 This transfer type also accesses the TLC local registers. However, the goal is to conduct a transfer using the
AHB interface.
 This transfer type also supports the following operations: