Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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3.5.6. SPI Interface Protocol

The SPI Interface block only supports SPI Mode 0:

• CPOL = 0, the base value (idle state) of the clock is 0.

• CPHA = 0, data is captured on the rising edge of the clock and driven on the falling edge of the clock.

A transaction consists of SPI_SS being driven low (active) by the SPI Master, and then driven high after all of the desired

bytes have been transferred. The SPI Interface assumes that all transfers consist of complete bytes. Any incomplete bytes

at the end of a transaction are ignored by the hardware. The EOS S3 Platform SPI Interface protocol supports several

different operations. The following sections describe these operations.

3.5.7. Basic Read/Write Transfers

For basic Read/Write transfers to the TLC registers, the EOS S3 platform SPI Interface protocol requires that the Address

Byte be transmitted first. The Address Byte includes a single Direction bit that represents the direction for the transfer

(write vs. read). As per SPI protocol, SPI_SLAVE_SSn is also required to be LOW when active SPI transactions are in

progress. The rising edge of SPI_SLAVE_CLK captures the data bits on SPI_SLAVE_MOSI and SPI_SLAVE_MISO pins.

The Direction bit is positioned in the Most Significant Bit (MSB) of the Address Byte. The value of the Direction bit is 1 for

write transactions, and 0 for read transactions. The remaining 7 bits represent the register address within the TLC

module, and this address is unique to the TLC module and should not be confused with M4-F addresses.

Examples:

• Read starting from TCL address 0x05 -> Address Byte = 0x05

• Write starting to TLC address 0x03 -> Address Byte = 0x83

During write transactions, the first byte received on the Master Out Slave In (SPI_SLAVE_MOSI) pin corresponds to the

Address Byte. The next bytes received correspond to Data Bytes. No valid data is driven on the Master In Slave Out

(SPI_SLAVE_MISO) pin. If the SPI clock is not free-running (for example, it does not toggle while SPI_SLAVE_SSN is

inactive), the hardware requires that there be at least two extra rising clock edges on the SPI clock following the

completion of a write transfer.

This ensures that the write data reaches its final destination. The simplest way to generate these extra clock cycles is to

perform a read from the TLC Scratch Byte Register (0x31). For more information, see Transfers to TLC Local Registers.

During read transactions, the first byte received on the SPI_SLAVE_MOSI pin corresponds to the Address Byte. The SPI

Interface ignores all subsequent data bits on the SPI_SLAVE_MOSI pin. Instead, following the Address Byte, the SPI

Interface begins to drive data on the SPI_SLAVE_MISO pin.

This begins by outputting two dummy bytes followed by the first Data Byte. Thereafter, each byte transmitted on the

SPI_SLAVE_MISO pin corresponds to valid Data Bytes. Unlike write transfers, read transfers do not require extra SPI clock

cycles after each transfer. The following figure shows an example of the SPI Interface protocol. In that use case, the MSB

bit is shifted out first.