Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 35
• SPI Master Interface provides the following:
 Operates as a Master only
 Supports up to three slaves
 Operates in mode 0 (this can be reprogrammed by M4)
 Supports a frame size of 8 (this can be reprogrammed by M4)
 Supports a maximum transfer size of 64K frames
 Supports little-endian data ordering
 Shifts out the most significant bit data first
 Supports DMA transfers
 Supports standard SPI protocol
• SPI Master Interface does not provide the following:
 Support for multiple SPI masters
 Support for other serial protocols (such as SSP or Microwire)
 Support for protocols that include DDR, dual, and quad transfers
• SPI Master Interface that is accessible by:
 Host Application Processor
 Configuration Logic
 On-chip programmable logic
• Configuration Logic is responsible for:
 Reading the external flash device
 Configuring its SPI transfer parameters using data stored within the external flash devices
 Confirming that the boot code is compatible with the EOS S3 device using stored values in the external
flash
 Loading the boot code into M4-F memory and enabling the M4-F execution once the boot code transfer
has completed
 Minimizing the elapsed time for booting the M4-F by using DMA transfers of boot code from the external
flash
 Posting status bits to the M4-F that aid in diagnosing the state of the boot process
3.5.3. Configuration Logic
The configuration logic consists of the following two parts:
• Configuration State Machine
• Configuration DMA logic
The Configuration State Machine provides control over retrieving boot code from an external flash device. To complete
this operation, the Configuration State Machine must configure and control the Configuration DMA and SPI Master
Interface.
The Configuration State machine programs the Configuration DMA and SPI Master Interface to access an external flash, by
performing the following operations:
• Setting the correct SPI clock rate
• Awakening the external Flash device from a low power state (such as a deep sleep modes)
• Examining the boot code parameters to optimize SPI Master transfers
• Initiating DMA loading of the M4-F boot code into M4-F memory