Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 33
3.4.11. Bit Command Controller
The Bit Command Controller handles the actual transmission of data and the generation of the specific levels for START,
Repeated START, and STOP signals by controlling the SCL and SDA lines.
The Byte Command Controller tells the Bit Command Controller which operation needs to be performed. For a single-
byte read, the Bit Command Controller receives eight separate read commands. Each bit-operation is divided into five
smaller pieces (idle and A, B, C, and D), except for a STOP operation which is divided into four smaller pieces (idle and A,
B, and C). The following figure illustrates the I
2
C bit command sequences.
Figure 11: I
2
C Bit Command Sequences
A B C D
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
Start
Rep
Start
Stop
Write
Read
3.4.12. Data I/O Shift Register
The DataIO Shift Register contains the data associated with the current transfer. During a read action, data is shifted in
from the SDA line. After a byte has been read, the contents are copied into the Receive Register. During a write action,
the contents of the Transmit Register are copied into the DataIO Shift Register and are then transmitted onto the SDA
line.
Serial Peripheral Interface (SPI)
The EOS S3 platform relies on three separate SPI interfaces.
• SPI Master for System Support
• SPI Master for Sensor Subsystem Support