Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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Figure 10: I

C Block Diagram

Pre-scale

Clock

Generator

Command

Status

Transmit

Receive

Wishbone Interface

SCL

SDA

The Sensor Manager uses the Wishbone interface to access the I

C Master during sensor data transfers.

3.4.9. Clock Generator

The Clock Generator generates an internal 4*Fscl clock enable signal that triggers all of the synchronous elements in the

Bit Command Controller. In addition, it also handles clock stretching required by some slaves.

3.4.10. Byte Command Controller

The Byte Command Controller handles I

C traffic at the byte level. It takes data from the Command Register and

translates it into sequences based on the transmission of a single byte. By setting the START, STOP, and READ bit in the

Command Register, the Byte Command Controller performs the following sequence:

• A START signal is generated

• The byte is read from the slave device

• A STOP signal is generated

Setting the START, STOP, and READ bits and the Byte Command Controller sequence starts a process that acts to divide each

byte operation into separate bit-operations, which are then sent to the Bit Command Controller.