Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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3.4.4. Slave Address Transfer

The first byte of data transferred by the master immediately after the START signal is the slave address. This is a 7-bit

calling address followed by a RW bit. The RW bit signals to the slave the data transfer direction. No two slaves in the

system can have the same address.

Only the slave with an address that matches the one transmitted by the master responds by returning an acknowledge

bit, which pulls SDA low at the ninth SCL clock cycle.

NOTE: The core supports 10-bit slave addresses by generating two address transfers. For details, see the Philips I

specifications.

The core treats a Slave address transfer like any other write action. The core stores the slave device address in the Transmit

3.4.5. Data Transfer

Once successful slave addressing has been achieved, the data transfer can proceed on a byte-by-byte basis in the direction

specified by the RW bit sent by the master. Each transferred byte is followed by an acknowledge bit on the ninth SCL

clock cycle. If the slave signals a No Acknowledge, the master can generate a STOP signal to abort the data transfer or

generate a Repeated START signal and start a new transfer cycle. If the master, as the receiving device, does not

acknowledge the slave, the slave releases the SDA line for the master to generate a STOP or Repeated START signal.

To write data to a slave, store the data to be transmitted in the Transmit Register and set the WR bit. To read data from a

slave, set the RD bit. During a transfer, the core sets the TIP flag, indicating that a transfer is in progress. When the

transfer is done, the TIP flag is reset, the IF flag is set, and when enabled, an interrupt is generated. The Receive Register

contains valid data after the IF flag has been set. The user can issue a new write or read command when the TIP flag is

reset.

3.4.6. STOP Signal

The master can terminate the communication by generating a STOP signal. A STOP signal, usually referred to as the P-

bit,

defined

low-to-high

transition

SDA

while

SCL

logical

3.4.7. Arbitration

The I

C Master block supports multi-master arbitration. However, this feature is not supported by other elements of the

EOS S3 platform.

3.4.8. I

C Core Architecture

The I

C core is built around the following four primary blocks (as shown in the following figure):

• Clock Generator

• Byte Command Controller

• Bit Command Controller

• DataIO Shift Register.

NOTE: All other blocks are involved with interfacing or for storing temporary values.