Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 30
• Arbitration lost interrupt, with automatic transfer cancellation
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus busy detection
• Supports 7-bit and 10-bit addressing mode
• Operates from a wide range of input clock frequencies
• Static synchronous design
• Fully synthesizable
The following sections describe the I
2
C system operations.
3.4.1. System Configuration
The I
2
C system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers. All devices connected to these
two signals must have open drain or open collector outputs. The logic AND function is exercised on both lines with
external pull-up resistors.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis, and each
data byte is 8 bits long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An
acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; as a result, the SDA line
can be changed only during the low period of SCL and must be held stable during the high period of SCL. A transition on the
SDA line while SCL is high is interpreted as a command (for details, see START Signal and STOP Signal).
3.4.2. I
2
C Protocol
Normally, standard communication consists of the following four parts:
• START signal generation
• Slave address transfer
• Data transfer
• STOP signal generation
The following figure illustrates an example of I
2
C protocol.
Figure 9: I
2
C Protocol Example
SDA
s
A7 A6 A5 A4
A3
A2
A1
RW
ACK
D7 D6 D5 D4 D3 D2 D1
D0
NACK
P
1 2 3 4 5 6 7 8 9 1
2
3 4 5 6 7 8 9
SCL
MSB MSBLSB
LSB
3.4.3. START Signal
When the bus is free/idle, this means no master device is engaging it (and both SCL and SDA lines are high), and the
master can initiate a transfer by sending a START signal. A START signal, usually referred to as the S-bit, is defined as a high-
to-low transition of SDA while SCL is high. The START signal denotes the beginning of a new data transfer.
A Repeated START is a START signal that is sent without first generating a STOP signal. The master uses this method to
communicate with another slave or with the same slave in a different transfer direction (for example, changing from
writing to a device to reading from a device) without releasing the bus.
The core generates a START signal when the STA-bit in the Command Register is set and the RD or WR bits are set.
Depending on the current SCL line status, it generates a START or Repeated START.