Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 29
I
2
C Master
There are two I
2
C Master modules in the EOS S3 device, and each one is assigned to a Sensor Manager module. The EOS
S3 platform also makes both of these I
2
C Master modules directly accessible to the EOS S3 platform internal bus system.
In each case, the I
2
C Master module provides the means for accessing devices on the associated I
2
C bus.
Figure 8: I2C Modules within the EOS S3 Platform
AHB Interface to M4
Control
Registers
SPI
Master
Interface
Sensor
Manager #0
(SM)
Sensor Processing
Subsystem (Simplified)
Wishbone
Bus #0
External I2C Bus #1
External SPI Bus
Wishbone
Bus #1
Sensor
Manager #1
(SM)
I2C
Master #1
Interface
I2C
Master #0
Interface
External I2C Bus #0
The I
2
C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between
devices. It is most suitable for applications that require occasional communication over a short distance between many
devices.
The I
2
C standard is a true multi-master bus that includes collision detection and arbitration to prevent data corruption if
two or more masters attempt to control the bus simultaneously.
The interface defines three transmission speeds:
• Normal: 100 Kbps
• Fast: 400 Kbps
• High speed: 3.5 Mbps
Only 100 Kbps (Normal) and 400 Kbps (Fast) modes are directly supported. The following features are available in the I
2
C
Master block:
• Compatible with the Philips I
2
C standard
• Multi-master operation
• Software-programmable clock frequency
• Clock stretching and wait state generation
• Software programmable acknowledge bit
• Interrupt or bit-polling driven byte-by-byte data-transfers