Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129

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Figure 4: Recommended External Debugger Connection for ARM DS Debugger

VDD

10 K

VTREF

SWDIO

SWCLK

SWO

nSRST

GND

Reset Circuit

RESET

SWO

SWCLK

SDWIO

ARM Processor/ASIC

22R

Signals from SWD connector

2.1.6. Debugger Bootstrap Configurations

Upon cold boot up, the M4-F DAP is enabled. The M4-F DBGEN is register-enabled by default and can be disabled later if

not needed. The M4-F DAP will only be reset during cold boot up (it is controlled by the POR from APC). The release of the

M4-F reset depends on the state of bootstrap pin IO_19. When it is strapped to high, the M4-F reset is released. When

strapped to low, the M4-F reset release depends on AP cfg_sm.

• Smartphone/High-Level O/S Wearable Configuration (Application Processor in System)

In a system with an application processor present, the application processor must drive bootstrap pin IO_19 to

indicate whether the Debugger is present. In this configuration, IO_19 is connected to the application processor

as part of the SPI interface (the IO_ 19 alternate function is SPIs_MOSI) and it must drive IO_19 during the de-

assertion of SYS_RSTn. Driving IO_19 high enables debugger support by releasing the M4-F from system reset

immediately. A debugger can take control of the system. Driving IO_19 low allows the system to boot normally,

which disallows the debugger access until after M4-F is released from reset. Once the M4-F is booted, the

debugger can be attached.

• Wearable Configuration (EOS S3 platform operating as Host)

In a wearable design, bootstrap pin IO_19 must always be strapped low to allow M4-F operation. Once the boot

code is downloaded and the M4-F is released from reset, the debugger can be attached to the system.