Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 23
Three of the 128 KB sub-blocks (384 KB) of the SRAM memory reside in the processor power domain. The CPU subsystem
must be powered on to access this memory space. Each 128 KB sub-block is addressed as four 32 KB segments (12
segments in total). An interrupt can be triggered when any of the 32 KB memory segments are accessed if the memory
is in a lower power state (deep sleep or shut down).
The last 128 KB SRAM sub-block resides in the Always-On power domain and can be accessed regardless of the state of
the processor subsystem power.
The 512 KB SRAM can be accessed by the following AHB Masters:
• M4-F system bus
• M4-F I-code bus
• M4-F D-code bus
• Application Processor (AP) through the SPI Slave Interface via the TLC
• Configuration DMA for SPI Flash Controller Master
• Voice DMA
• System DMA
• FFE
The SRAM clocks are dynamically controlled. When there is no activity on the memory, the clocks are gated off to ensure
lower power consumption.
2.1.5. Development Support (Serial Wire Interface)
Depending on overall EOS S3 platform setup and requirements, two different Serial Wire interfaces can be selected. The
external debugger can be connected to either IO_14/IO_15 or IO_44/IO_45, based on the bootstrap pin IO_8 (see
Bootstrap Modes). The two signals are serial wire clock and serial wire data. The optional serial wire viewer can be
selected from several different pins.
2.1.5.1. Debugger Configuration
The recommend external configuration if using ARM DS debugger is shown in the following figure. Other debuggers may
have different recommendations.