Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 22
 IEEE 754-compliant operations on single-precision, 32-bit, floating point values
 32-bit instructions for single-precision (C float) data-processing operations
 Combined Multiply and Accumulative instructions for increased precision (Fused MAC)
 Hardware support for denormals and all IEEE rounding modes
 32 dedicated 32-bit single-precision registers, also addressable as 16 double-word registers
 Decoupled three-stage pipeline
• NVIC closely integrated with the processor core to achieve low-latency interrupt processing
 External interrupts, configurable from 1 to 240
 Bits of priority, configurable from 3 to 8
 Dynamic reprioritization of interrupts
 Priority grouping, enabling selection of preempting and non-preempting interrupt levels
 Support for tail-chaining and late arrival of interrupts, enabling back-to-back interrupt processing without
the overhead of state saving and restoration between interrupts
 Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction
overhead
 Optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support
• An optional MPU
 Eight memory regions
 Sub-Region Disable (SRD), enabling efficient use of memory regions
 The ability to enable a background region that implements the default memory map attributes
• Bus interfaces
 Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: I-Code, D-Code, and System bus
interfaces
 Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface
 Bit-band support that includes atomic bit-band read and write operations
 Memory access alignment
 Write buffer for buffering of write data
 Exclusive access transfers for multiprocessor systems
• Low-cost debug solution that features:
 Debug access to all memory and registers in the system, including access to memory mapped devices,
access to internal core registers when the core is halted, and access to debug control registers even while
SYS_RSTn is asserted
 Serial Wire Debug Port (SW-DP) debug access
 Flash Patch Breakpoint (FPB) unit for implementing breakpoints and code patches
 Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
 Instrumentation Trace Macrocell (ITM) for support of printf() style debugging
 Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA), including Single Wire Output
(SWO) mode
2.1.4. Embedded SRAM
The M4-F processor subsystem has up to 512 KB of embedded SRAM that is divided into four sub-blocks of 128 KB each.
Each sub-block is accessible simultaneously via four independent AHB busses. Each 128 KB sub-block is further divided
down in four 32 KB segments (16 segments in total).