Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 21
implements a version of the Thumb
®
, an instruction set based on Thumb-2 technology, ensuring high code density and
reduced program memory requirements. The M4-F instruction set provides the exceptional performance expected of a
modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The M4-F instruction set provides the exceptional performance that is expected of a modern 32-bit architecture, with the
high code density of 8-bit and 16-bit microcontrollers. The Cortex M4-F processor closely integrates a configurable NVIC, to
deliver industry-leading interrupt performance. The NVIC includes a Non-Maskable Interrupt (NMI) that can provide up
to 256 interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of Interrupt Service Routines (ISRs),
dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability
to suspend load-multiple and store-multiple operations.
Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tool-chain
optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power
designs, the NVIC integrates with the sleep modes, which includes an optional deep sleep function. This enables the
entire device to be rapidly powered down while still retaining program state.
2.1.1. System-Level Interface
The M4-F processor provides multiple interfaces using AMBA
®
technology to provide high speed, low latency memory
accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral
controls, system spinlocks and thread-safe Boolean data handling.
The M4-F processor has a Memory Protection Unit (MPU) that permits control of individual regions in memory, enabling
applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task basis.
Such requirements are becoming critical in many embedded applications such as automotive.
2.1.2. Integrated Configurable Debug
The M4-F processor can implement a complete hardware debug solution. This provides high system visibility of the
processor and memory through a 2-pin SWD port.
For system trace the processor integrates an Instrumentation Trace Macrocell™ (ITM) alongside data watchpoints and a
profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer
(SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin.
2.1.3. M4-F and Core Peripherals
The M4-F processor provides the following features:
• A low gate count processor core with low latency interrupt processing that includes:
 A subset of the Thumb instruction set, defined in the ARMv7-M Architecture Reference Manual
 Banked Stack Pointer (SP)
 Hardware integer divide instructions, SDIV and UDIV
 Handler and thread modes
 Thumb and debug states
 Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low interrupt latency
 Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and
exit
 Support for ARMv6 big-endian byte-invariant or little-endian accesses
 Support for ARMv6 unaligned accesses
• Floating Point Unit (FPU) providing: