Datasheet

© 2020 QuickLogic Corporation www.quicklogic.com 20
2. M4-F Processor Subsystem
Subsystem Overview
The M4-F 32-bit processor subsystem is one of the primary computation blocks of the EOS platform (shown in the
following figure) and includes:
• Optional features such as a Nested Vectored Interrupt Controller (NVIC), flash patch, etc.
• Up to 512 KB SRAM
• Peripheral bus incorporating:
  UART
  Watchdog Timer
  Timers
Figure 3: Cortex M4-F Block Diagram
Cortex M4-F
Processor
Nested Vectored
Interrupt
Controller (NVIC)
Flash Patch
Breakpoint
(FPB)
AHB
Access Port
(AHB-AP)
Cortex-M4
Core
Floating Point
Unit (FPU)
Bus Matrix
Data Watchpoint
And Trace
(DWT)
Instrumentation
Trace Macrocell
(ITM)
Interrupts and
Power Control
Wake-Up Interrupt
Controller (WIC)
Serial Wire
Debug Port
(SW-DP)
Serial Wire
Debug Interface
ICode AHB-Lite
Instruction Interface
DCode AHB-Lite
Data Interface
System AHB-Lite
System Interface
Memory
Protection Unit
(MPU)
Trace Port
Interface Unit
(TPIU)
Trace Port Interface
The M4-F processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it
ideal for demanding embedded applications. The processor delivers exceptional power efficiency using an efficient
instruction set and extensively optimized design. This combination provides high-end processing hardware that includes
optional IEEE754-compliant single-precision floating-point computation, and a range of single-cycle and SIMD
multiplication and multiply-with-accumulate capabilities, that ensure saturating arithmetic and dedicated hardware
division.
To aid in designing of cost-sensitive devices, the M4-F processor implements tightly-coupled system components that
reduce processor area while significantly improving interrupt handling and system debug capabilities. The M4-F processor