Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 18
Resolution of 1 msec
I
2
C Master and
Configurable I
2
C/SPI
Interface
I
2
C Master and SPI Master with programmable clock pre-scaler
Option to disable multi-master support and slave-inserted wait for shorter SCL cycles
Configurable for two I
2
C Masters or one I
2
C Master and one SPI Master
Other Interfaces SPI Master for interfacing with serial flash memories and other external SPI-based
peripherals of up to 20 MHz
I
2
S Slave transmitter for downloading audio samples to host application processor
UART Serial support for M4-F debug and code development Communication with UART-based
external peripherals
Other Peripherals Timers
Watchdogs
8-bit GPIO controller
ADC Low sampling rate (12-bit)
LDO Regulators On-chip LDO for system logic
Separate on-board LDO for memory
Integrated Software
Debug Interface
2-pin SWD port for access to the following memory mapped resources:
M4-F internal registers and memories
FFE and Sensor Manager memories
FFE control registers
On-chip programmable logic memories
On-chip programmable logic designs through generic AHB bus
All memory map peripherals such as timers, WDT, SPI Master, etc.
I
2
C Master used for I
2
C sensor debug
Multiplexed dedicated parallel debug interface
Packaging Options 42-ball WLCSP (2.66 mm x 2.42 mm x 0.51 mm) (27 user I/Os and 2 VCCIO banks)
64-ball BGA (3.5 mm x 3.5 mm x 0.71 mm) (46 user I/Os and 2 VCCIO banks)
Note: Not all cores (FFE, eFPGA, LPSD) are available in all devices. Refer to the part numbers table for the correct part
number