Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 17
The following table lists the top-level features. This feature set enables the EOS S3 platform to support use cases in the
smartphone and wearable device markets.
Table 1 : EOS S3 Platform Supported Features
Feature Details
M4-F Subsystem Cortex M4-F processor with floating point unit support (M4-F)
Embedded SRAM (up to 512 KBytes) for code and data memory
Vectored interrupt support
Wakeup interrupt controller
2-pin SWD port
FFE 50 KB control memory
16 KB data memory
Single cycle MAC
Digital Microphone
Support
I
2
S microphone
PDM microphone
On-chip PDM-to-PCM conversion
Hardware bypass path for PDM interface to host application processor and/or Voice
CODEC
Integrated LPSD from Sensory
Packet FIFOs Batching
Memory
128 KBytes of M4-F SRAM can be used as HiFi sensor batching memory
Multiple packet FIFOs to support the FFE to application processor/M4-F data transfers:
8 KBytes packet FIFO with ring-buffer mode support
one 256x32 packet FIFO and two 128x32 packet FIFOs
Power Management Unit Low-power mode with fast wake-up
Programmable power modes (deep sleep, sleep with retention, and active)
Multiple power domains
Power sequencing for sleep and wake-up entry and exit
Firmware and hardware-initiated sleep entry
Wake-up triggers via internal and external events
On-chip Programmable
Logic
2,400 effective logic cells with 64 Kbits of RAM, 8 RAM FIFO controllers and 2 GPIO
banks
Supports SPI Slave configuration
Supports reconfiguration from M4-F
Supports five clocks
32 kHz Oscillator with
Real-Time Clock (RTC)
32 kHz crystal oscillator (external crystal required) with bypass option
1 Hz clock generation with compensation register
RTC function with one alarm register
Start time of 500 ms
High Frequency Clock
Source
Programmable frequency (2 MHz to 80 MHz) for better frequency resolution
Calibrated output (using 32 kHz input)
Startup time of 410 µs
Clock divider can be programmed in 12 bits
System DMA 16-channel DMA allows efficient data movement between processing elements
SPI Slave SPI Slave application processor communication of up to 20 MHz
Time Stamping Automatic hardware time stamp on every sensor read in the interrupt mode
Up to eight sensor interrupt captured time-stamps (8-bit)
Main time stamp of 30 bits for M4-F processor and 24 bits for FFE