Datasheet

© 2020 QuickLogic Corporation www.quicklogic.com 13
QuickLogic EOS S3 Ultra Low Power multicore MCU
Platform Highlights
Multi-Core, Ultra Low Power Sensor and Audio Processing Platform Enabling
Always-On, Always-Aware Application
Multi-Core Design
• Ultra-low power µDSP-like Flexible Fusion
Engine (FFE) for always-on, real-time sensor
fusion algorithms, an ARM
®
Cortex
®
M4-F
floating point processor for general purpose
processing, and on-chip programmable logic
for flexibility and integration of additional
logic functions to a single device
• Multiple, concurrent cores enable algorithm
partitioning capability to achieve the most
power and computationally efficient sensor
processing system-on-a-chip (SoC) in the
market
Cortex M4-F Processor
• Up to 80 MHz operating frequency
• Up to 512 KB SRAM with multiple power
modes, including deep sleep (128 KB of this
memory can be used for HiFi sensor batching)
• Ideal for computationally intensive sensor
processing algorithms (continuous heart rate
monitor, indoor navigation, always-on voice
recognition, etc.)
Third-Generation Flexible Fusion
Engine
• Up to 10 MHz operating frequency
• 50 KB control memory
• 16 KB data memory
• µDSP-like architecture for efficient
mathematical computations
• Ideal for always-on, real-time sensor fusion
algorithms (such as pedometer, activity
classification, gesture recognition, and others)
Sensor Manager
• 1.5 KB x 18-bit memory
• Completely autonomous (zero load on M4-F)
initialization and sampling of sensors through
hard-wire I2C or configurable I2C/SPI interface
• Dramatically lowers the power consumption
associated with sensor data acquisition
Communication Manager
Communicates with host applications processor
through the SPI Slave interface of up to 20 MHz
Dedicated Voice Support
• Audio support for Pulse Density Modulation
(PDM) or I2S microphones
• Optional hardware PDM bypass path to
forward microphone data to application
processor or Voice CODEC
• Dedicated logic for PDM to Pulse Code
Modulation (PCM) conversion
• Dedicated hard logic integration of Sensory
Low Power Sound Detect (LPSD) for on-chip
voice recognition
On-Chip Programmable Logic
• 2,400 effective logic cells with 64 Kbits of RAM
available
• Eight RAM FIFO controllers
• Provides capability to add logic functions or
augment existing logic functions
Operating System Support
Android 6.0 compliant