Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 108
The following table lists the standby current for LDO bypass with external voltage supplied.
Table 48: Standby Current
a
Power Mode 1.1V 1.0V Units
Standby 32K DS 20.683 17.52 µA
Standby 64K DS 23.967 19.69
Standby 128K DS 28.833 23.83
Standby 512K DS 59.303 49.0
FPGA 60.0 42.0
a. Standby with SRAM blocks in Deep Sleep (DS). FPGA in low power mode
with retention.
The following table lists the CoreMark current consumption at varying frequencies.
Table 49: CoreMark Current Values
Frequency in MHz VDD 1.1V VDD 1.0V Units
80 84 75 µA/MHz
40 86 77
The following table lists the EOS S3 power consumption under various conditions.
Table 50: EOS S3 Power Measurements
Mode EOS S3 Power
VDD at 1.0 V
EOS S3 Power
AVDD at 1.8V
Comments
Cortex-M4 with FPU 75 µW/MHz 31µW Running CoreMark (HSOSC@20 MHz)
Flexible fusion engine 30 µW/MHz 31µW Running the QuickLogic PCG algorithm
(HSOSC@20 MHz)
Always-on voice listening
Mode
97 µW 23µW PDM microphone interface and LPSD Active
and Listening (HSOSC@2.1 MHz)
Always-on voice running a
fixed trigger
387 µW 31µW Assumes 12 MIPS on M4, LPSD Active 100%
of the time, M4-F wakes up 30% of the time to
check for a fixed trigger (HSOSC@20 MHz)