Datasheet

QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation www.quicklogic.com 105
Clock and Oscillator Characteristics
Table 40: Clock and Oscillator Characteristics
a,b
Symbol Min. Typ. Max. Unit
XTAL_IN 16 32.768 - kHz
HOSC 2 20 80 MHz
HOSC Accuracy
b
-1 +1 %
HOSC Frequency Variant
b
-3 +3 %
SPI Master CLK 2 10 20 MHz
SPI Slave CLK 2 10 20 MHz
SWD CLK 2 5 10 MHz
Voice SS (APB Clock) - - 10 MHz
PDM Left Clock - - 5 MHz
PDM Right Clock - - 5 MHz
I
2
S Clock
- - 5 MHz
LPSD Clock - - 1 MHz
FPGA Clock
c
- - 72 MHz
a
Maximum frequency is with VDD at 1.1V, ±10%.
b
Programmed HOSC Frequency > 10MHz
c
Using onboard HOSC
Output Rise/Fall Time
NOTE: The multi-functional IOs also have programmable slew rates (SRs). The two states are SR = 0 (slow) or SR = 1 (fast)
and can be programmed from A0 registers.
11.4.1. Output Rise/Fall Time (VCCIO = 1.8V)
Table 41: Output Rise/Fall Time (SR = 1, VCCIO = 1.8 V)
Transition D[1] D[0] C
LOAD
Min. Typ. Max. Units
Rise Time
PAD↑ (10% to
90%)
0 0 2pF 0.71 1.27 2.23 ns
0 1 5pF 0.65 1.18 2.16 ns
1 0 10pF 0.67 1.24 2.30 ns
1 1 20pF 0.84 1.51 2.81 ns
Fall Time,
PAD↓ (90% to
10%)
0 0 2pF 0.60 1.02 1.80 ns
0 1 5pF 0.57 0.96 1.80 ns
1 0 10pF 0.70 1.18 2.14 ns
1 1 20pF 0.84 1.39 2.51 ns