Datasheet
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129
© 2020 QuickLogic Corporation
www.quicklogic.com 103
HSOSC High speed oscillator frequency 2 20 80 MHz
CMOS Clock Duty Cycle CMOS clock duty cycle 40 50 60 Percent
CMOS Clock Input Jitter CMOS clock input jitter - - 280 ns
a.
See
Low Dropout Regulators
for an explanation of the different LDO configurations.
b.
Except where indicated, Min and Max values are tested on 100% of the device at 25°C.
c.
Typical values are based on 25°C and nominal voltage (VDD1=VDD2=1.1V, VCCIO=1.8V).
d.
Device bootup and initialization should be at 1.1V, and minimum of 1.05V to come out of Power-On reset in LDO Bypass mode.
e.
LDO1_VIN and LDO2_VIN must be the same voltage.
f.
Special analog pad with CMOS tolerant input.
g.
The OSCin/out pads are connected to an AVDD supply. Additional current consumption is drawn through the pin
when OSCin high level is higher than AVDD.
Table 35: Weak Pull-Up/Pull-Down Characteristics
Parameter Symbol Condition Min. Typ. Max. Unit
Weak Pull-Up Current
I
PU
VDDIO = 3.3V VDDIO =
2.5V VDDIO = 1.8V
37
19
16
64
35
32
1
59
58
µA
Weak Pull-Down Current
I
PD
VDDIO = 3.3V VDDIO =
2.5V VDDIO = 1.8V
29
14
15
59
31
31
105
59
56
µA
Input Leakage
I
IH
/I
IL
- - <1 µA
Short Circuit Current
I
OSH
VDDIO = 3.3V VDDIO =
2.5V VDDIO = 1.8V
- 116
72
69
- mA
Short Circuit Current
I
OSL
VDDIO = 3.3V VDDIO =
2.5V VDDIO = 1.8V
- 109
74
68
- mA
Table 36: DC Input and Output Levels
a
Symbol
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V
MIN
V
MAX
V
MIN
V
MAX
V
MAX
V
MIN
mA mA
LVTTL -0.3 0.8 2.2 VDDIO + 0.3 0.4 2.4 2.0 –2.0
LVCMOS25 -0.3 0.7 1.7 VDDIO + 0.3 0.4 1.8 2.0 –2.0
LVCMOS18 -0.3 0.63 1.17 VDDIO + 0.3 0.45 VCCIO - 0.45 2.0 –2.0
a.
The data in this table represents JEDEC specifications. QuickLogic devices either meet or exceed these
requirements. Based on weak pull-down I/O termination disabled.