QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Contact Information E-mail: info@quicklogic.com Sales: America-sales@quicklogic.com Europe-sales@quicklogic.com Asia-sales@quicklogic.com Japan-sales@quicklogic.com Korea-sales@quicklogic.com Support: www.quicklogic.com/support Internet: www.quicklogic.com Notice of Disclaimer QuickLogic is providing this design, product or intellectual property, ‘as is’.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Contents QuickLogic EOS S3 Ultra Low Power multicore MCU Platform Highlights .................. 13 1. Functional Overview ...................................................................................................... 15 EOS S3 Ultra Low Power multicore MCU Platform Architecture ............................................ 15 2. M4-F Processor Subsystem ..................................................................
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 3.5.5. SPI Slave ............................................................................................................................................. 36 3.5.6. SPI Interface Protocol ......................................................................................................................... 38 3.5.7. Basic Read/Write Transfers ...............................................................................
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 6.2.1. FIFO Controller .................................................................................................................................... 58 6.2.2. Configurable Input/Output Signals ...................................................................................................... 58 6.2.3. Multipliers .........................................................................................................
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 System DMA.......................................................................................................................... 86 9.2.1. Functional Description ......................................................................................................................... 86 9.2.2. SDMA Configurations ................................................................................................................
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 15. Revision History......................................................................................................... 116 © 2020 QuickLogic Corporation www.quicklogic.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figures Figure 1: EOS S3 Ultra Low Power multicore MCU Platform Architecture....................................... 15 Figure 2: EOS S3 Ultra Low Power multicore MCU Platform Block Diagram................................... 19 Figure 3: Cortex M4-F Block Diagram .............................................................................................
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 49: Bootstrap Timing ............................................................................................................ 82 Figure 50: PKFB Block Diagram ..................................................................................................... 84 Figure 51: System DMA Block Diagram ..........................................................................................
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Tables Table 1: EOS S3 Platform Supported Features............................................................................... 17 Table 2: I2C Master AC Timing ....................................................................................................... 52 Table 3: I2S Timing .........................................................................................................................
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Table 48: Standby Currenta .......................................................................................................... 108 Table 49: CoreMark Current Values.............................................................................................. 108 Table 50: EOS S3 Power Measurements......................................................................................
QuickLogic EOS S3 Ultra Low Power multicore MCU Platform Highlights Multi-Core, Ultra Low Power Sensor and Audio Processing Platform Enabling Always-On, Always-Aware Application initialization and sampling of sensors through hard-wire I2C or configurable I2C/SPI interface Multi-Core Design • • Ultra-low power µDSP-like Flexible Fusion Engine (FFE) for always-on, real-time sensor fusion algorithms, an ARM® Cortex® M4-F floating point processor for general purpose processing, and on-chip programmable logic
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Additional Features • On-device circuit to support 32.
1. Functional Overview The QuickLogic® EOS™ S3 platform is a multi-core, ultra-low power sensor processing system designed for mobile market applications such as smartphone, wearable, and Internet of Things (IoT) devices. The core of the EOS S3 platform is its proprietary µDSP-like Flexible Fusion Engine (FFE). To complement the FFE, the EOS S3 platform also includes a Cortex M4-F subsystem that enables higher level, general purpose processing.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d © 2020 QuickLogic Corporation 27-129 www.quicklogic.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 The following table lists the top-level features. This feature set enables the EOS S3 platform to support use cases in the smartphone and wearable device markets.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 The following figure shows a more detailed view of the datapaths within the EOS S3 Ultra Low Power multicore MCU platform.
2. M4-F Processor Subsystem Subsystem Overview The M4-F 32-bit processor subsystem is one of the primary computation blocks of the EOS platform (shown in the following figure) and includes: • Optional features such as a Nested Vectored Interrupt Controller (NVIC), flash patch, etc.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 implements a version of the Thumb®, an instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The M4-F instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Three of the 128 KB sub-blocks (384 KB) of the SRAM memory reside in the processor power domain. The CPU subsystem must be powered on to access this memory space. Each 128 KB sub-block is addressed as four 32 KB segments (12 segments in total). An interrupt can be triggered when any of the 32 KB memory segments are accessed if the memory is in a lower power state (deep sleep or shut down).
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 4: Recommended External Debugger Connection for ARM DS Debugger 10 K 10 K 10 K 0R VDD ARM Processor/ASIC VTREF Signals from SWD connector 22R SWDIO SDWIO SWCLK SWCLK 22R SWO SWO nSRST Reset Circuit RESET GND GND 2.1.6. Debugger Bootstrap Configurations Upon cold boot up, the M4-F DAP is enabled. The M4-F DBGEN is register-enabled by default and can be disabled later if not needed.
3. Sensor Processing Subsystem Overview The Sensor Processing Subsystem provides the EOS S3 device with the ability to perform sensor fusion operations while using low overall power. The following figure illustrates the architecture of this module.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Flexible Fusion Engine The FFE is responsible for the following: • Coordinating the operation of the Sensor Manager(s) • Retrieval of sensor data retrieved by the Sensor Manager(s) • Sensor fusion calculations • • Transferring the results of the sensor fusion calculations to the EOS S3 platform Coordinating FFE operations with on-chip programmable logic IP.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 values retrieved from Sensor Manager Memory. • Sending the results of the Sensor Fusion calculations to the EOS S3 platform. The FFE can use either the Packet FIFO interface or the AHB Master port to pass packets of sensor data to the EOS S3 platform • Coordinating FFE operations with on-chip programmable logic-based IP. This IP waits for a Start signal from the EOS S3 system prior to beginning processing. 3.2.2.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 7: Sensor Manager Architecture Sensor Manager (SM) Instruction and Data Memory Microcontroller Unit (MCU) The Sensor Manager consists of two parts: • • Microcontroller Unit Instruction and Data Memory 3.3.1. Microcontroller Unit The Microcontroller Unit (MCU) is responsible for the operation of the Sensor Manager.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 I2C Master There are two I2C Master modules in the EOS S3 device, and each one is assigned to a Sensor Manager module. The EOS S3 platform also makes both of these I2C Master modules directly accessible to the EOS S3 platform internal bus system. In each case, the I2C Master module provides the means for accessing devices on the associated I2C bus.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d • Arbitration lost interrupt, with automatic transfer cancellation • Start/Stop/Repeated Start/Acknowledge generation • Start/Stop/Repeated Start detection • Bus busy detection • Supports 7-bit and 10-bit addressing mode • Operates from a wide range of input clock frequencies • Static synchronous design • Fully synthesizable 27-129 The following sections describe the I2C system operations. 3.4.1.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 3.4.4. Slave Address Transfer The first byte of data transferred by the master immediately after the START signal is the slave address. This is a 7-bit calling address followed by a RW bit. The RW bit signals to the slave the data transfer direction. No two slaves in the system can have the same address.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 10: I2C Block Diagram Pre-scale Register Clock Generator Command Register SCL Status Register SDA Transmit Register Receive Register Wishbone Interface The Sensor Manager uses the Wishbone interface to access the I2C Master during sensor data transfers. 3.4.9.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 3.4.11. Bit Command Controller The Bit Command Controller handles the actual transmission of data and the generation of the specific levels for START, Repeated START, and STOP signals by controlling the SCL and SDA lines. The Byte Command Controller tells the Bit Command Controller which operation needs to be performed. For a singlebyte read, the Bit Command Controller receives eight separate read commands.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d • 27-129 SPI Slave The following sections describe each of these interfaces. 3.5.1. SPI Master for System Support IP within the on-chip programmable logic can directly access the SPI Master for system support interface. The following figure shows this connection.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d • 27-129 Enabling M4-F operations As a part of this process, the Configuration State Machine examines the EOS S3 device ID in the boot flash data. If this device ID is incorrect, the Configuration State Machine halts the boot process, and this boot process can only be restarted by asserting a reset. 3.5.4.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d • 27-129 Retrieving run-time data Both of these operations are possible during either Smart Phone or Wearable EOS S3 modes. However, in a typical Wearable application, there is no local Host to use the SPI Slave interface. Therefore, the following description is primarily focused on the Smart Phone mode of operation.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 3.5.6. SPI Interface Protocol The SPI Interface block only supports SPI Mode 0: • CPOL = 0, the base value (idle state) of the clock is 0. • CPHA = 0, data is captured on the rising edge of the clock and driven on the falling edge of the clock. A transaction consists of SPI_SS being driven low (active) by the SPI Master, and then driven high after all of the desired bytes have been transferred.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 15: SPI Slave Protocol Diagram Read/Write Bit 0 - Read 1 - Write MSB 7 6 5 4 3 2 1 0 LSB MOSI Address Data In 1 Data In 1 ... Data In n MISO X X X X X MOSI Address X X X X X MISO X Dummy Dummy Data Out 0 ... Data Out n SPI Write SPI Read 3.5.8. Device ID Read The Device ID transfer cycle is a special protocol cycle for identifying the EOS S3 device to the Host SPI controller.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 – Burst write transfers to the M4-F Memory space – Burst read transfers from the M4-F Memory space 3.5.10. Transfers to TLC Local Registers This transfer type depends upon the type of TLC register being accessed. The default TLC response is to increment automatically the TLC register address (not the M4-F Memory space address) after each byte accessed (for example, as in a read from the M4-F Memory Address registers).
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 register, the Memory Address Byte 0 – 1 registers are automatically incremented. In addition, the TLC registers address loops back to point to the first data byte register, Memory Data Byte 0. By doing this, a block of data may be written from a single SPI data stream (for example, one address phase followed by a series of data phases representing the burst data).
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 The following figure shows the basic SPI write operation under mode 11 (CPOL = 1, CPHA = 1). Figure 19: Basic SPI Write Operation (Mode 11) SPI_CSn SPI_CLK MOSI R/W AD6 AD5 AD4 AD3 AD2 AD1 AD0 MISO DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Z Tri-state 3.5.15. SPI Read Cycle The following figure shows the basic SPI read operation under mode 11 (CPOL = 1, CPHA = 1).
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 21: SPI Multiple Read Operation (Mode 11) SPI_CSn SPI_CLK MOSI R/W AD6 AD5 AD4 AD3 AD2 AD1 AD0 MOSI DI/07DI/06DI/05DI/04DI/ 03DI/02DI/01DI/O0 Register Address (ADDR) DI/07DI/06DI/05DI/04DI/ 03DI/02DI/01DI/O0 DI/07DI/06DI/05DI/ 04DI/03DI /02DI/01DI/O0 Data 2 (from ADDR) Data 3 (from ADDR) Data 1 (from ADDR) DI/07DI/06DI/05DI/04DI/ 03DI/02DI/01DI/O0 Data 4 (from ADDR) 3.5.17.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 If the SPI interface is intended to support additional devices, such as SPI-based ACDs for measuring the output of additional sensor types, then the number of potential non-byte aligned shift sequences increases significantly. For example, the SPI transfer sequence corresponding to the AD7091 low power, 12-bit ADC is shown in the following figure.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 25: SPI Block Diagram Master SPI Shift Register Baud Rate Register Slave SPI MISO MISO MOSI MOSI SCK SCK SS Shift Register SS 3.5.20.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 26: SPI Clock Format 0 (CPHA = 0) Idle State Ends Transfer Transfer Begins 1 SCK Edge Nr.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double-buffered; data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 AHB Master Bridge The FFE AHB Master Bridge gives the Sensor Processing Subsystem FFE the ability to write directly to some of the EOS S3 platform resources. The following figure shows that this interface is composed of four functional units.
4. Voice Subsystem The integrated Voice Subsystem shown in the following figure is designed to support always-on voice capability and has been optimized to work with Sensory TrulyHandsfree™ Voice Control voice recognition software. The EOS S3 platform supports two types of digital microphones. Both types of microphones are supported in mono and stereo configuration.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 PCM samples by PDM2PCM block. Low Power Sound Detect Support To minimize power associated with always on voice processing, the EOS S3 platform supports acoustic activity detection using LPSD hardware. This allows normal PDM or I2S microphones from any vendor to get power savings associated with the LPSD hardware. When enabled, the EOS S3 platform can send PCM samples from left or right microphone to the LPSD hardware.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 30: I2S Slave Port AHB2 APB M AON Bus Matrix S I2S_APB Bridge SDMA SCLK WS_SLV I2S Slave SDO © 2020 QuickLogic Corporation DONE[0] TX_EMP_0_INTR M4 REQ[0] www.quicklogic.
5. Timing I2C Master AC Timing The following figure shows the I2C Master AC timing. Figure 31: I2C Master AC Timing tHD:DAT tLOW SCL SDA tHD:STA tSU:DAT tSU:STO SCL SDA tHIGH tBUF The following figure describes the I2C Master AC timing parameters. Table 2: I2C Master AC Timing Symbol Description Standard Mode Min. Fast Mode Max. Min. Units Max. fSCL Operating frequency. - 100 - 400 kHz tLOW Clock low period. 4.7 - 1.30 - µs tHIGH Clock high period. 4.0 - 0.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 32: I2S Timing Waveform fCLK tLOW tLOW Serial Clock (SCK) tSU:SETUP Word Select (WS) Data In LSB tOH:OUTHOLD tD:DE LAY tH:HOLD MSB Data Out LSB MSB Table 3: I2S Timing Symbol Parameter Min. Typ. Max.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Table 4: PDM Microphone Timing Symbol Parameter Min. Typ. Max. Units fCLK PDM Frequency - - 10 MHz tSU Data Input Set Up Time 10 - - ns tH Data Input Hold Time 1 - - ns fCLK Duty Cycle 48 50 52 % SPI Timing 5.4.1. SPI Master The following figure illustrates the SPI Master timing.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 5.4.2. SPI Slave The following figure illustrates the SPI Slave timing. Figure 35: SPI Slave Timing f t CLK LOW t HIGH SCL t CS:SETUP t CSn t DO:DELAY DI:SETUP t DI:HOLD t CS:HOLD MOSI t t CS:BUF DO:HOLD MISO The following table lists the SPI Slave timing. Table 6: SPI Slave Timing Symbol Parameter Min. Max. Units fCLK SPI Clock - 20 MHz tLOW SPI Clock Low Time 22.
6. On-Chip Programmable Logic The on-chip programmable logic provides flexibility to the EOS S3 platform for implementing additional functions. The on-chip programmable logic consists of multiplexor-based logic cells, built-in RAM modules and FIFO controllers, builtin multipliers, as well as interfaces with I/O drivers of the EOS S3 device. The major features of the embedded on-chip programmable logic are listed in the following figure.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 RAM/FIFO The on-chip programmable logic also includes up to eight instances of 8K (9,216 bits) dual-port RAM modules for implementing RAM and FIFO functions.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 37: On-Chip Programmable Logic Configurable Input/Output ESEL RST IE EN D R Q OSEL OUT OQI D OQE E R Q IZ FIX_HOLD IN IQZ Q IQE E R D 6.2.3. Multipliers Built-in signed multipliers are also available in the on-chip programmable logic. The multiplier relieves the use of logic to implement such functions. There are two instances embedded in the on-chip programmable logic.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 38: On-Chip Programmable Logic Multiplier Valid_mul_0 Sel_mul_32x32 Scan_mode A_mult[31:0] [63:32] L B_mult[31:0] A[31:0] [31:0] 32x32 Multiplier B[31:0] C[31:0] C_mult[31:0] C[63:32] L C_mult[63:32] [15:0] [63:48] L [15:0] A[15:0] [47:32] B[15:0] 16x16 Multiplier C[31:0] L [31:16] C_mult[63:0] [31:16] L [31:16] A[15:0] [15:0] 16x16 Multiplier C[31:0] B[15:0] L © 2020 QuickLogic Corporation www.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Interface to the On-Chip Programmable Logic IP within the on-chip programmable logic can use the following interfaces to communicate with resources outside of the chip. These include: • EOS S3 Platform • SPI Master Interface for System Support • Sensor Processing Subsystem • Packet FIFO These resources help the IP to coordinate its activities with other modules in the EOS S3 platform.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 6.3.3. SDMA Interface The EOS S3 platform provides a System DMA (SDMA) module for use by various components. The purpose for the SDMA function is to avoid loading the Host processor with simple data movement operations, and to conduct data movement during periods when the Host Processor is in a low-power state.
7. Power Management Power Supply Modes and Schemes In the EOS S3 platform, there are 31 power islands, which includes the always-on domain. All of the power domains can be independently powered on and off by power management logic, with the exception of the always-on power domain. This allows for additional power savings obtained using software and hardware control through PMU registers.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Low Dropout Regulators The EOS S3 platform has two on-chip low dropout regulators (LDOs). One LDO is for SRAM, and the other LDO is for digital logic. By having a separate regulator for the SRAM, the SRAM voltage can be further reduced to save power consumption. Table 11: LDO Regulators LDO Maximum Current Output Voltage Range LDO-1 for SRAM 50 mA 1.057 V – 1.132 V LDO-2 for Digital Logic 30 mA 1.057 V – 1.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 41: Use Case 2: Single Voltage Rail 1.62 V – 3.6 V 1.057 V – 1.132 V 1.62 V – 3.6 V 1.057 V – 1.132 V 7.3.3. Use Case 3: External Voltage Supplied In this example, the EOS S3 platform LDOs are bypassed and the SRAMs and logic gates are externally supplied through VDD1 and VDD2 pads. The LDO_VIN, VDD2, and VDD1 pads are tied together on the board and connected to the supply voltage.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Power-On Sequence of CMOS Clock The recommended power-on sequence of the EOS S3 when CMOS clock is used as input to XTAL_IN is shown in the following figure. Figure 43: Power-On Sequence of CMOS Clock 32.768 kHz Clock XTAL_IN PAD(8) [Pull Down] XTAL_OUT PAD(9) [Pull Down] AVDD LDO_VIN/VDD1/VDD2 VCCIO 1 µs (Min) CMOS Clock (32 kHz) 2 ms (Max) 300 µs (Min.) 300 µs (Min.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Table 12: Power-On Sequence Timing Parameters Letter Parameter Condition Min. Typ. Max.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 44: Current Measurement Scheme with External Power Supplies IDD_VDD LDO_VIN, VDD1, VDD2 DC + – IDD_AVDD AVDD DC + – IDD_VCCIOA VCCIOA DC + – IDD_VCCIOB VCCIOB DC + – The following two tables list the current measurement on each supply rail for different power-on sequences in LDO bypass mode (external voltage supply). All I/Os and dedicated pins are tri-stated, and all external caps are removed.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Power-Down Sequence of CMOS Clock The recommended power-down sequence of the EOS S3 when CMOS clock is used as input to XTAL_IN is shown in the following figure. Figure 45: Power-Down Sequence of CMOS Clock A 3 ms (Min) AVDD LDO_VIN/VDD1/ VDD2 VCCIO CMOS Clock (32 kHz) B 2 ms (Min) NOTE: Recommended power down sequence: VCCIO > VDD/AVDD. Power down VCCIO before VDD.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Table 17: LDO Mode Typical Inrush Currenta Mode Data (mA) AVDD @ 1.8 V 0.013 VCCIOA @ 1.8 V 3.662 VCCIOA @ 3.3 V 65.640 VCCIOB @ 1.8 V 51.630 VCCIOB @ 3.3 V 114.000 LDOVIN @ 1.1 V 4.000 a. All IOs are tri-stated or not driven, including SYS_RSTn. Table 18: LDO Bypass Mode Typical Inrush Current Mode Data (mA) AVDD @ 1.8V 0.020 AVDD @ 3.3V 0.023 VCCIOA @ 1.8V 7.598 VCCIOA @ 3.3V 77.610 VCCIOB @ 1.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Power-On Sequence of Crystal Clock The recommended power-on sequence of the EOS S3 when crystal clock is used as input to XTAL_IN is shown in the following figure. Figure 46: Power-On Sequence of Crystal Clock 32.768 kHz Clock XTAL_IN PAD(8) [Pull Down] XTAL_OUT PAD(9) [Pull Down] AVDD LDO_VIN/VDD1/VDD2 VCCIO CRYSTAL IN 2 ms (Max.) XTAL_IN 300 µs (Min.) 300 µs (Min.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Table 20: Power-On Sequence Timing Parameters Letter Parameter Condition Min. Typ. Max.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Power-Down Sequence of Crystal Clock The recommended power-down sequence of the EOS S3 when crystal clock is used as input to XTAL_IN is shown in the following figure. Figure 47: Power-Down Sequence of Crystal Clock AVDD A LDO_VIN/VDD1/ VDD2 VCCIO Crystal Clock (32 kHz) NOTE: Recommended power down sequence: VCCIO > VDD/AVDD. Power down VCCIO before VDD. Powering down all power supplies at same time is allowed.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Clocks and Resets 7.8.1. Clocks The EOS S3 platform contains 19 clock domains, and most clock domains have their own register-controlled divider. Each clock domain has one or more clock paths that it supports. Clock paths can be individually gated. See the following table for a full listing of clock domains.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 48: Clock Tree © 2020 QuickLogic Corporation www.quicklogic.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 For Clock domains 01, 09 and 10, the clock phase is locked, but the frequency may be different, such as Clock domain C30 and C31. For Clock C08X4 and C08X1, the clock phase is locked and the frequency of C08X1 is always one-fourth of C08X4 clock frequency. Most Clock paths can be gated by software independently, the exceptions are Clock C00_P0, C01_P0, C10_HCLK_P0, C10_FCLK_P0, C20_P0 and C23_P0.
8. Other EOS S3 Platform Features Multi-Function Inputs/Outputs (IOs) There are 46 I/Os for the BGA and 27 I/Os for the WLCSP package that can be muxed for various functions. Each I/O output can have up to 4 different functional outputs. Each functional input can be selected from up to 8 different I/Os. The controls for I/Os (such as output enable, drive strength, etc.) can be controlled from three different sources; the A0 registers, the on-chip programmable logic and other sources (such as M4-F, FFE, etc.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d • 27-129 one at the interrupt source, the other at the top-level interrupt controller. AP: Interrupt mechanism for the AP is the same as M4, but with a different mask. All interrupt sources are muxed to a single, combined interrupt before being sent to the AP. 8.4.2. Interrupt Sources Interrupts sourced from each subsystem functional blocks get combined into one interrupt for each subsystem.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d • • 27-129 DMIC Voice Off — Interrupt is triggered when HW Loss of Voice is detected by DMIC. LPSD Voice Off — Interrupt is triggered when Loss of Voice is detected by LPSD. DMAC0 Block Done — DMAC0 finished transfer of a block size of data. DMAC1 Block Done — DMAC1 finished transfer of a block size of data. DMAC0 Buffer Done — DMAC0 finished transfer of a buffer size of data.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d • Reset Interrupt • FFE Message • FFE Combined • AP Boot • LDOs Power Good Interrupts • SRAM Timeout • LPSD Voice Detect • DMIC Voice Detect • SDMA DONE Channel 1–11 27-129 NOTE: SDMA Channel 0 (I2S Slave) does not wake up the M4-F. Bootstrap Modes The EOS S3 device I/O configuration options are selected by pulling special bootstrap pins high or low, which are latched upon de-assertion of the SYS_RSTn pin.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 8.6.1. Internal/External HSO Configuration The configuration of internal or external High-Speed Oscillator (HSO) is configured by bootstrap pins IO_8 and IO_9. When selecting the External HSO, the external clock is provided on IO_6.
9. Other Peripherals Packet FIFO The packet FIFO bank provides data buffering for data transfers between FFE and/or on-chip programmable logic and/or M4-F to AP and/or M4-F. It is composed of four packet FIFOs of differing sizes. A typical use case may have the FFE push sensor data as packets into the Packet FIFO. When a specific threshold is reached, the programmable interrupt signals to the M4-F or AP to pop off the data for additional processing.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 The FIFO instances are listed in the following table. Table 28: Packet FIFO Instances Instance Depth Width Description FIFO_8K 4096 17 Supports normal or packet FIFO modes. Supports ring buffer mode support (16-bit data, 1-bit SOP). Drainer logic with programmable threshold to implement ring buffer function. PUSH source: FFEs or M4-F. POP destination: AP or M4-F.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 As with FIFO_8K, these FIFOs provide the FIFO word count on the pop side. FIFO word counts specify the exact number of words in the FIFO regardless of packet boundaries. The AP or M4-F is expected to read the FIFO word count, and pop no more than the count allows. In this way, the empty flag signal is never used to throttle the pop of data.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 power. The SDMA can support a hardware/software request, and DMA requests can be from a peripheral or initiated by software. The SDMA uses an AHB-Lite Master port for reading DMA descriptors from 128x32 bits SRAM and transferring data from source to destination and the SDMA AHB Master port is connected to the Always-On AHB bus matrix so that it can transfer data even when M4-F power domain is in deep sleep or shut down.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 The System DMA can perform the following tasks: • Transfer voice data from M4-F SRAM to I2S Slave. • Transfer data from M4-F SRAM to FFE CM (swapping). • Transfer data from M4-F SRAM to FFE DM. • Transfer data from FFE DM to M4-F SRAM. • Transfer data from M4-F SRAM to on-chip programmable logic. • Transfer data from on-chip programmable logic to M4-F SRAM. 9.2.2.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 9.3.2. Functional Description In brief, the ADC voltage measurement core includes an input multiplexer, a delta-sigma modulator, and a digital control core. The digital control core controls the analog blocks power up/down sequences, generates the delta-sigma control signals and implements the output decimation. 9.3.3. Electrical Characteristics The following table lists the key electrical characteristics for the ADC module.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 54: Example Voltage Divider Circuit Battery Voltage R3 M2 PMOS R1 ADC Input M1 NMOS R2 ADC Measurement Enable The voltage divider resistors, R1 and R2 must be chosen according to the amount of voltage scaling required. It is left to software to scale the ADC values to best determine the proper corresponding battery voltage level.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 55: Timer Block Diagram Sleep Mode FFE Pending PD or WU Time Out Configuration FFE Kick Off 32 or 16 KHz Clock PMU Kick Off Error Configurations Time Value for FFE Time Stamp x8 for FFE Masked INT x8 INT x8 x8 INT Mask x8 9.5.1.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 57: PMU and FFE Timing Waveform Event CNT 1 ms CNT 0 3 2 1 1 0 3 2 2 1 0 3 2 3 1 0 3 2 0 1 0 3 2 1 0 1 ms Event PMU Kick Off FFE Kick Off © 2020 QuickLogic Corporation www.quicklogic.
10. Device Characteristics Pinout and Pin Description The following table lists the input and output (I/O) locations and functions for each of the IO pins in EOS S3. It is important to note two things: • There is at least one default function assigned to each IO (and its default = 0) • The EOS S3 software does not configure the IO if it is being used as a default NOTE: Table 28 lists the default functions in bold for all EOS S3 IO pins in the Alternate Functions column.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 IO_18 IO VCCIOB -- E8 38 FBIO_18, SWV, DEBUG_MON_0, GPIO(4), SENSOR_INT_1 IO_19 IO VCCIOB C1 H8 36 FBIO_19, SPI_SLAVE_MOSI, UART_RTS Note: IO_19 can serve as bootstrap for debugger mode as an M4-F reset release mechanism.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 IO<37> VCCIO -- G2 Z Z IO<38> VCCIO E6 E2 Z Z IO<39> VCCIO F6 H2 Z Z IO<40> VCCIO -- D2 Z Z IO<41> VCCIO -- F1 Z Z IO<42> VCCIO -- H1 Z Z IO<43> VCCIO D7 D1 Z Z IO<44> VCCIO E7 E1 Z IO<8>=1; IO<8>=0 IO<45> VCCIO F7 G1 Z IO<8>=1; IO<8>=0 © 2020 QuickLogic Corporation www.quicklogic.
11. Electrical Specifications DC Characteristics The DC specifications are provided in Table 33 through Table 36. Table 33: Absolute Maximum Ratings Parameter Value Parameter Value LDO Input Voltage -0.5 V to 3.6 V ESD Pad Protection 2 kV VDD Voltage -0.5 V to 1.26 V –55°C to + 125°C AVDD/VDDIO Voltage -0.5 V to 3.6 V Laminate Package (BGA) Storage Temperature Input Voltage -0.5 V to 3.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 HSOSC High speed oscillator frequency 2 20 80 MHz CMOS Clock Duty Cycle CMOS clock duty cycle 40 50 60 Percent CMOS Clock Input Jitter CMOS clock input jitter - - 280 ns a. See Low Dropout Regulators for an explanation of the different LDO configurations. b. Except where indicated, Min and Max values are tested on 100% of the device at 25°C. c.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Output Drive Current NOTE: The multi-functional IOs have four programmable drive strength states D[1-0]: D00=2 mA, D01=4 mA, D10=8 mA, D11= 12 mA. The drive strength can be set by programming A0 registers. Table 37: Output Drive Current (VDD = 1.8V) in mA Parameter IOH Condition D[1] VOH = VDD – 0.4 IOL VOL = 0.4 D[0] Min. Typ. Max. 0 0 3.42 5.83 9.16 0 1 6.84 11.7 18.3 1 0 9.12 15.5 24.4 1 1 12.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Clock and Oscillator Characteristics Table 40: Clock and Oscillator Characteristicsa,b Symbol Min. XTAL_IN HOSC HOSC Accuracy b HOSC Frequency Variant b Typ. Max. Unit 16 32.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Table 42: Output Rise/Fall Time (SR = 0, VCCIO = 1.8V) Transition Rise Time PAD↑ (10% to 90%) Fall Time, PAD↓ (90% to 10%) D[1] D[0] CLOAD Min. Typ. Max. Units 0 0 2pF 0.74 1.30 2.28 ns 0 1 5pF 0.70 1.24 2.26 ns 1 0 10pF 0.77 1.36 2.50 ns 1 1 20pF 0.92 1.63 2.97 ns 0 0 2pF 0.65 1.13 1.97 ns 0 1 5pF 0.71 1.20 2.13 ns 1 0 10pF 0.84 1.41 2.47 ns 1 1 20pF 1.00 1.66 2.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 11.4.3. Output Rise/Fall Time (VCCIO = 3.3V) Table 45: Output Rise/Fall Time (SR = 1, VCCIO = 3.3V) Transition Rise Time PAD↑ (10% to 90%) Fall Time, PAD↓ (90% to 10%) D[1] D[0] CLOAD Min. Typ. Max. Units 0 0 2pF 0.63 0.86 1.42 ns 0 1 5pF 0.57 0.93 1.57 ns 1 0 10pF 0.64 1.04 1.76 ns 1 1 20pF 0.88 1.36 2.25 ns 0 0 2pF 0.59 0.78 1.32 ns 0 1 5pF 0.52 0.81 1.37 ns 1 0 10pF 0.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 The following table lists the standby current for LDO bypass with external voltage supplied. Table 48: Standby Currenta Power Mode 1.1V 1.0V Standby 32K DS 20.683 17.52 Standby 64K DS 23.967 19.69 Standby 128K DS 28.833 23.83 Standby 512K DS 59.303 49.0 FPGA 60.0 42.0 Units µA a. Standby with SRAM blocks in Deep Sleep (DS). FPGA in low power mode with retention.
12. Application Examples Smartphone or High-Level O/S Wearable Design The following figure illustrates the EOS S3 platform as a discrete sensor hub, offloading the always-on, real-time processing from the Application Processor. The voice subsystem is enabled, it handles the always-on voice recognition. The hardware bypass path on the PDM interface enables voice recognition to be offloaded to the EOS S3 platform, and then normal voice communication to be handed off seamlessly to the dedicated voice CODEC.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Figure 59: Example of a Real-Time Operating System Wearable Design Buzzer/Speaker 32 kHz ON/OFF Battery ADC UART Debug GPIO Sensor INT BLE/WiFi SPI Slave I2C EOS S3 Sensor Voice Sensor UART GNSS PDM I2S SPI Master Flash BLE/WiFi Optional © 2020 QuickLogic Corporation www.quicklogic.
13. Package Information 42-Ball WLCSP Package Drawing Figure 60: 42-Ball WLCSP Package Drawing © 2020 QuickLogic Corporation www.quicklogic.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 64-Ball BGA Package Drawing Figure 61: 64-Ball BGA Package Drawing © 2020 QuickLogic Corporation www.quicklogic.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 64-Pin QFN Package Drawing Note: QFN package information is provided as reference for QuickFeather board only. This package is not available mass production. Figure 62: 64-Pin QFN Package Drawing © 2020 QuickLogic Corporation www.quicklogic.
14. Soldering Information Reflow Profile QuickLogic follows IPC/JEDEC J-STD-020 specification for lead-free devices. The following figure shows the Pb-free component preconditioning reflow profile. Figure 63: Pb-Free Component Preconditioning Reflow Profile The following table lists the Pb-free component preconditioning reflow profile. Table 51: Pb-Free Component Preconditioning Reflow Profilea, b Profile Feature Profile Conditions Average ramp-up rate (Tsmax) to Tp) 3 °C per sec. max.
QuickLogic EOS S3 Ultra Low Power multicore MCU datasheet - Version 3.3d 27-129 Package Thermal Characteristics The EOS S3 Ultra Low Power multicore MCU platform is available for Commercial (–20 °C to 85 °C) junction temperature ranges.
15. Revision History Version Date Revision 3.3d June 2020 Update maximum FPGA Clock Frequency (table 19 and table 37) 3.3c May 2020 Add QFN IO and package information for QuickFeather board reference 3.3b April 2020 Add product table 3.3a March 2020 Remove 64-Pin QFN package information; update description for SFBIO (table 28) and change the description for device IO (table 29). 3.
