User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 94 of 909 2019 Ambiq Micro, Inc.

3.6 Debug Interfaces

A number of useful debug facilities are provided in the Apollo3 Blue MCU.

3.6.1 Debugger Attachment

An external debugger can be connected to the MCU using ARM’s Serial Wire Debug (SWD) interface. The

SWD interface is a 2-wire interface that is supported by a variety of off-the-shelf commercial debuggers,

enabling customers to utilize their development environment of choice.

3.6.2 Instrumentation Trace Macrocell (ITM)

For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data

watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system events these

generate, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace,

and profiling information through a single pin.

3.6.3 Trace Port Interface Unit (TPIU)

The Apollo3 Blue MCU includes a Cortex-M4 Trace Port Interface Unit (TPIU). The Cortex-M4 TPIU is an

ARM IP component that acts as a bridge between the on-chip trace data from the ITM and the single pin

supporting the Serial Wire Viewer Protocol.

The TPIU includes a Trace Output Serializer that can format and send the SWV protocol in either a

Manchester encoded form or as a standard UART stream.

3.6.4 Faulting Address Trapping Hardware

The Apollo3 Blue MCU offers an optional facility for trapping the address associated with bus faults

occurring on any of the three AMBA AHB buses on the chip. This facility must be specifically enabled so

that energy is not wasted when one is not actively debugging.

3.7 ITM Registers

ARM ITM Registers.

INSTANCE 0 BASE ADDRESS:0xE0000000

2:0 DTCMEN 0x0 RW

Enable DTCM power-on status event

NONE = 0x0 - Do not enable DTCM power-on status event

GROUP0DTCM0EN = 0x1 - Enable GROUP0_DTCM0 power on status

event

GROUP0DTCM1EN = 0x2 - Enable GROUP0_DTCM1 power on status

event

GROUP0EN = 0x3 - Enable DTCMs in group0 power on status event

GROUP1EN = 0x4 - Enable DTCMs in group1 power on status event

ALL = 0x7 - Enable all DTCM power on status event

Table 30: MEMPWREVENTEN Register Bits

Bit Name Reset RW Description