User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 92 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
3.5.3.1.2.12MEMPWREVENTEN Register
Event enable register to control which MEMPWRSTATUS bits are routed to event input of CPU.
OFFSET: 0x0000002C
INSTANCE 0 ADDRESS: 0x4002102C
This register controls which power enable for the memories will result in an event to the CPU. It includes all
the power on status for the memory domains. If any bits are set, then if the domain is turned on, it will result
in an event to the ARM core.
8 BLELEVEN 0x0 RW
Control BLE power-on status event
EN = 0x1 - Enable BLE power-on status event
DIS = 0x0 - Disable BLE power-on status event
7 PDMEVEN 0x0 RW
Control PDM power-on status event
EN = 0x1 - Enable PDM power-on status event
DIS = 0x0 - Disable PDM power-on status event
6 MSPIEVEN 0x0 RW
Control MSPI power-on status event
EN = 0x1 - Enable MSPI power-on status event
DIS = 0x0 - Disable MSPI power-on status event
5 ADCEVEN 0x0 RW
Control ADC power-on status event
EN = 0x1 - Enable ADC power-on status event
DIS = 0x0 - Disable ADC power-on status event
4 HCPCEVEN 0x0 RW
Control HCPC power-on status event
EN = 0x1 - Enable HCPC power-on status event
DIS = 0x0 - Disable HCPC power-on status event
3 HCPBEVEN 0x0 RW
Control HCPB power-on status event
EN = 0x1 - Enable HCPB power-on status event
DIS = 0x0 - Disable HCPB power-on status event
2 HCPAEVEN 0x0 RW
Control HCPA power-on status event
EN = 0x1 - Enable HCPA power-on status event
DIS = 0x0 - Disable HCPA power-on status event
1 MCUHEVEN 0x0 RW
Control MCUH power-on status event
EN = 0x1 - Enable MCHU power-on status event
DIS = 0x0 - Disable MCUH power-on status event
0 MCULEVEN 0x0 RW
Control MCUL power-on status event
EN = 0x1 - Enable MCUL power-on status event
DIS = 0x0 - Disable MCUL power-on status event
Table 28: DEVPWREVENTEN Register Bits
Bit Name Reset RW Description